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Intel CK408 Mobile Clock Synthesizer
CY28339
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07507 Rev. *A
Revised June 25, 2004
Features
• Compliant with Intel® CK 408 rev 1.1 Mobile Clock
Synthesizer specifications
• 3.3V power supply
• Two differential CPU clocks
• Nine copies of PCI clocks
• Three copies configurable PCI free-running clocks
• Two 48 MHz clocks (USB, DOT)
• Five/six copies of 3V66 clocks
•One VCH clock
• One reference clock at 14.318 MHz
• SMBus support with read-back capabilities
• Ideal Lexmark profile Spread Spectrum electromag-
netic interference (EMI) reduction
• Dial-a-Frequency™ features
• Dial-a-dB™ features
• 48-pin TSSOP package
Note:
1.
TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up,
a 0 state will be latched into the device’s internal state register.
Table 1. Frequency Table[1]
S2
S1
CPU (1:2)
3V66
66BUFF(0:2)/
3V66(0:4)
66IN/3V66–5
PCIF, PCI
REF
USB/ DOT
1
0
100M
66M
66IN
66-MHz clock input
66IN/2
14.318M
48M
1
1
133M
66M
66IN
66-MHZ clock input
66IN/2
14.318M
48M
0
0
100M
66M
66M
66M
33 M
14.318M
48M
0
1
133M
66M
66M
66M
33 M
14.318M
48M
M
0
TCLK/2
TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
TCLK/2
Pin Configuration
Block Diagram
VDD_REF
CPUT1:2
CPUC1:2
PCIF
XTAL
PLL Ref Freq
X2
X1
REF
VDD_PCI
USB (48MHz)
VCH_CLK/ 3V66_1
OSC
VDD_CPU
CPU_STOP#
SCLK
PCI0:2
PCI_STOP#
Stop
Clock
Control
Stop
Clock
Control
PLL 1
SMBus
Logic
DOT (48MHz)
PD#
S1:2
VDD_48MHz
SDATA
VDD_3V66
3V66_0:1
3V66_2:4/
Divider
Network
3V66_5/ 66IN
PWR
PWR
PWR
PWR
PWR
PLL 2
PWR
66BUFF0:2
Gate
VTT_PWRGD##
/2
Top View
1
2
3
4
5
6
7
8
9
10
11
12
25
28
27
XIN
26
13
14
15
16
17
18
19
20
21
22
23
24
37
36
35
34
33
29
30
31
32
40
39
38
XOUT
GND_REF
PCI7
41
44
43
42
45
48
47
46
PCI2
66BUFF0/3V66_2
GND_CORE
SCLK
GND_48 MHz
CPUT2
CPU_STOP#
GND_PCI
VDD_3V66
66IN/3V66_5
3V66_0
USB_48MHz
CPUC1
VDD_REF
PCI8
PCIF
PCI0
PCI1
VDD_PCI
PCI4
PCI5
PCI6
GND_3V66
66BUFF1/3V66_3
66BUFF2/3V66_4
PD#
VDD_CORE
VTT_PWRGD#
SDATA
GND_3V66
VDD_3V66
PCI_STOP#
3V66_1/VCH
VDD_48 MHz
DOT_48MHz
S2
IREF
CPUC2
VDD_CPU
GND_CPU
CPUT1
VDD_CPU
S1
REF
PCI4:8
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