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LH28F800BGHB-BL85 Datasheet(PDF) 8 Page - Sharp Corporation |
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LH28F800BGHB-BL85 Datasheet(HTML) 8 Page - Sharp Corporation |
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8 / 43 page  LH28F800BG-L/BGH-L (FOR TSOP, CSP) 2 PRINCIPLES OF OPERATION The LH28F800BG-L/BGH-L SmartVoltage flash memories include an on-chip WSM to manage block erase and word write functions. It allows for : 100% TTL-level control inputs, fixed power supplies during block erasure and word write, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power-down mode (see Table 2 "Bus Operations"), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erasure and word writing. All functions associated with altering memory contents—block erase, word write, status and identifier codes—are accessed via the CUI and verified through the status register. Commands are written using standard micro- processor write timings. The CUI contents serve as input to the WSM, which controls the block erase and word write. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. Interface software that initiates and polls progress of block erase and word write can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspended. Word write suspend allows system software to suspend a word write to read data from any other flash memory array location. 2.1 Data Protection Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases or word writes are required) or hardwired to VPPH1/2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPP ≤ VPPLK, memory contents cannot be altered. The CUI, with two-step block erase or word write command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is at VIL. The device’s boot blocks locking capability for WP# provides additional protection from inadvertent code or data alteration by block erase and word write operations. 3 BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes or status register independent of the VPP voltage. RP# can be at either VIH or VHH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power- down mode, the device automatically resets to read array mode. Five control pins dictate the data flow in and out of the component : CE#, OE#, WE#, RP# and WP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the - 8 - |
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