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AD9244BST-40 Datasheet(PDF) 4 Page - Analog Devices |
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AD9244BST-40 Datasheet(HTML) 4 Page - Analog Devices |
4 / 37 page AD9244 Rev. C | Page 3 of 36 SPECIFICATIONS DC SPECIFICATIONS AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), differential clock inputs, VREF = 2 V, external reference, differential analog inputs, unless otherwise noted. Table 1. Test AD9244BST-65 AD9244BST-40 Parameter Temp Level Min Typ Max Min Typ Max Unit RESOLUTION Full VI 14 14 Bits DC ACCURACY No Missing Codes Full VI Guaranteed Guaranteed Bits Offset Error Full VI ±0.3 ±1.4 ±0.3 ±1.4 % FSR Gain Error1 Full VI ±0.6 ±2.0 ±0.6 ±2.0 % FSR Differential Nonlinearity (DNL)2 Full VI ±1.0 ±1.0 LSB 25°C V ±0.7 ±0.6 LSB Integral Nonlinearity (INL)2 Full V ±1.4 ±1.3 LSB Full VI −4 +4 −4 +4 LSB TEMPERATURE DRIFT Offset Error Full V ±2.0 ±2.0 ppm/°C Gain Error (EXT VREF)1 Full V ±2.3 ±2.3 ppm/°C Gain Error (INT VREF)3 Full V ±25 ±25 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage Error (2 VREF) Full VI ±29 ±29 mV Load Regulation @ 1 mA Full V 0.5 0.5 mV Output Voltage Error (1 VREF) Full IV ±15 ±15 mV Load Regulation @ 0.5 mA Full V 0.25 0.25 mV Input Resistance Full V 5 5 kΩ INPUT REFERRED NOISE VREF = 2 V 25°C V 0.8 0.8 LSB rms VREF = 1 V 25°C V 1.5 1.5 LSB rms ANALOG INPUT Input Voltage Range (Differential) VREF = 2 V Full V 2 2 V p-p VREF = 1 V Full V 1 1 V p-p Common-Mode Voltage Full V 0.5 4 0.5 4 V Input Capacitance4 25°C V 10 10 pF Input Bias Current5 25°C V 500 500 μA Analog Bandwidth (Full Power) 25°C V 750 750 MHz POWER SUPPLIES Supply Voltages AVDD Full IV 4.75 5 5.25 4.75 5 5.25 V DRVDD Full IV 2.7 5.25 2.7 5.25 V Supply Current IAVDD Full V 109 64 mA IDRVDD Full V 12 8 mA PSRR Full V ±0.05 ±0.05 % FSR POWER CONSUMPTION DC Input6 Full V 550 300 mW Sine Wave Input Full VI 590 640 345 370 mW 1 Gain error is based on the ADC only (with a fixed 2.0 V external reference). 2 Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit. 3 Includes internal voltage reference error. 4 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 7 for the equivalent analog input structure. 5 Input bias current is due to the input looking like a resistor that is dependent on the clock rate. 6 Measured with dc input at maximum clock rate. |
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