bq2022

SLUS526B − OCTOBER 2002 − REVISED OCTOBER 2003

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An 8-bit CRC of the command byte and address bytes is computed by the bq2022 and read back by the host

to confirm that the correct command word and starting address were received. If the CRC read by the host is

incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the

host is correct, the host issues read time slots and receives data from the bq2022 starting at the initial address

and continuing until the end of a 32-byte page is reached. At that point the host sends eight additional read time

slots and receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from

the initial starting byte to the last byte of the current page. Once the 8-bit CRC has been received, data is again

read from the 1024-bit EPROM data field starting at the next page. This sequence continues until the final page

and its accompanying CRC are read by the host. Thus each page of data can be considered to be 33 bytes

long, the 32 bytes of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at

the end of each page.

Initialization and

ROM Command

Sequence

READ

MEMORY/Generate

CRC Command

C3h

Address Low Byte

A0

A7

Address High Byte

A8

A15

EPROM Memory and CRC

Byte Generated at 32-Byte

Page Boundaries

NOTE:Individual bytes of address and data are transmitted LSB first.

Figure 7. READ MEMORY/Page CRC

READ MEMORY/Field CRC

To read memory without CRC generation on 32 byte page boundaries, the ROM command is followed by the

READ MEMORY command, F0h, followed by the address low byte and then the address high byte.

NOTE: As shown in Figure 8, individual bytes of address and data are transmitted LSB first.

An 8-bit CRC of the command byte and address bytes is computed by the bq2022 and read back by the host

to confirm that the correct command word and starting address were received. If the CRC read by the host is

incorrect, a reset pulse must be issued and the entire sequence must be repeated. If the CRC received by the

host is correct, the host issues read time slots and receives data from the bq2022 starting at the initial address

and continuing until the end of the 1024-bit data field is reached or until a reset pulse is issued. If reading occurs

through the end of memory space, the host may issue eight additional read time slots and the bq2022 responds

with a 8-bit CRC of all data bytes read from the initial starting byte through the last byte of memory. After the

CRC is received by the host, any subsequent read time slots appear as logical 1s until a reset pulse is issued.

Any reads ended by a reset pulse prior to reaching the end of memory does not have the 8-bit CRC available.

Initialization and

ROM Command

Sequence

READ

MEMORY

Command

F0h

Address Low

Byte

A0

A7

Address High

Byte

A8

A15

Read and

Verify CRC

Read EEPROM

Memory Until End

of EPROM Memory

Read and

Verify CRC

Figure 8. READ MEMORY/Field CRC

WRITE MEMORY

The WRITE MEMORY command is used to program the 1024-bit EPROM memory field. The 1024-bit memory

field is programmed in 8-byte segments. Data is first written into an 8-byte RAM buffer one byte at a time. The

contents of the RAM buffer is then ANDed with the contents of the EPROM memory field when the programming

command is issued.

Figure 9 illustrates the sequence of events for programming the EPROM memory field. After issuing a ROM

command, the host issues the WRITE MEMORY command, 0Fh, followed by the low byte and then the high

byte of the starting address. The bq2022 calculates and transmits an 8-bit CRC based on the WRITE command

and address.