AD10242

–10–

THEORY OF OPERATION

Refer to the functional block diagram. The AD10242 employs

three monolithic ADI components per channel (AD9632, OP279,

and AD9042), along with multiple passive resistor networks

and decoupling capacitors to fully integrate a complete 12-bit

analog-to-digital converter.

The input signal is first passed through a precision laser trimmed

resistor divider, allowing the user to externally select operation

with a full-scale signal of

±0.5 V, ±1.0 V, or ±2.0 V by choosing

the proper input terminal for the application. The result of

the resistor divider is to apply a full-scale input of approximately

0.4 V to the noninverting input of the internal AD9632 amplifier.

The AD9632 provides the dc-coupled level shift circuit required

for operation with the AD9042 ADC. Configuring the amplifier

in a noninverting mode, the ac signal gain can be trimmed to

provide a constant input to the ADC centered around the inter-

nal reference voltage of the AD9042. This allows the converter

to be used in multiple system applications without the need for

external gain and level shift circuitry normally requiring trim.

The AD9632 was chosen for its superior ac performance and

input drive capabilities. These two specifications have limited

the ability of many amplifiers to drive high performance ADCs.

As new amplifiers are developed, pin compatible improve-

ments are planned to incorporate the latest operational ampli-

fier technology.

The OP279 provides the buffer and inversion of the internal

reference of the AD9042 in order to supply the summing node

of the AD9632 input amplifier. This dc voltage is then summed

with the input voltage and applied to the input of the AD9042

ADC. The reference voltage of the AD9042 is designed to track

internal offsets and drifts of the ADC and is used to ensure

matching over an extended temperature range of operation.

APPLYING THE AD10242

Encoding the AD10242

The AD10242 is designed to interface with TTL and CMOS

logic families. The source used to drive the ENCODE pin(s)

must be clean and free from jitter. Sources with excessive jitter

will limit SNR and overall performance.

0.01 F

TTL OR CMOS

SOURCE

ENCODE

ENCODE

AD10242

Figure 6. Single-Ended TTL/CMOS Encode

The AD10242 encode inputs are connected to a differential

input stage (see Figure 4). With no input connected to either

the ENCODE or

ENCODE input, the voltage dividers bias the

inputs to 1.6 V. For TTL or CMOS usage, the encode source

should be connected to ENCODE (Pins 29 and/or 51).

ENCODE

(Pins 28 and/or 52) should be decoupled using a low inductance

or microwave chip capacitor to ground. Devices such as AVX

05085C103MA15, a 0.01

µF capacitor, work well.

Performance Improvements

It is possible to improve the performance of the AD10242

slightly by taking advantage of the internal characteristics of the

amplifier and converter combination. By increasing the 5 V

supply slightly, the user may be able to gain up to a 5 dB improve-

ment in SFDR over the entire frequency range of the converter.

It is not recommended to exceed 5.5 V on the analog supplies

since there are no performance benefits beyond that range and

care should be taken to avoid the absolute maximum ratings.

ANALOG INPUT FREQUENCY – MHz

60

0

510

40

20

ENCODE = 40MSPS

SNR (dB)

30

50

10

20

29.2

34.5

52.5

60.95

70

80

SFDR (dBFS)

INPUT FREQUENCY – MHz

0.5

3.0

05

2.0

1.5

1.0

2.5

10

15

20

25

30

40

0

–0.5

45

50

55

35

ENCODE = 40MSPS

TPC 14. Gain Flatness vs. Input Frequency

REV. D