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SN65LVDS388A Datasheet(PDF) 11 Page - Texas Instruments |
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SN65LVDS388A Datasheet(HTML) 11 Page - Texas Instruments |
11 / 19 page www.ti.com APPLICATION INFORMATION Host Controller TX Clock LVDS Drivers Target Controller Target Indicates twisting of the conductors. T T T T T Indicates the line termination circuit. Host Balanced Interconnect Power Power DB0 DB1 DB2 DBn–3 T T T T DBn–2 DBn–1 DBn RX Clock DB0 DB1 DB2 DBn–3 DBn–2 DBn–1 DBn LVDx368, LVDx388 LVDx388A, or LVDx390 ANALOG AND DIGITAL GROUNDS/POWER SUPPLIES FAIL SAFE SN65LVDS386/388A/390, SN65LVDT386/388A/390 SN75LVDS386/388A/390, SN75LVDT386/388A/390 SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004 Figure 12. Typical Application Schematic Although it is not necessary to separate out the analog/digital supplies and grounds on the SN65LVDS/T388A and SN75LVDS/T388A, the pinout provides the user that option. To help minimize or perhaps eliminate switching noise being coupled between the two supplies, the user could lay out separate supply and ground planes for the designated pinout. Most applications probably have all grounds connected together and all power supplies connected together. This configuration was used while characterizing and setting the data-sheet parameters. One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV, and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors, as shown in Figure 13. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level, regardless of the differential input voltage. 11 |
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