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AD73311L Datasheet(PDF) 19 Page - Analog Devices |
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AD73311L Datasheet(HTML) 19 Page - Analog Devices |
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19 / 37 page  REV. A AD73311L –18– ANALOG LOOP-BACK SELECT INVERT SINGLE- ENDED ENABLE +6/–15dB PGA CONTINUOUS TIME LOW-PASS FILTER REFCAP REFOUT REFERENCE 0/38dB PGA VREF VINN VINP AD73311L VOUTP VOUTN Figure 12. Analog Loop-Back Connectivity INTERFACING The AD73311L can be interfaced to most modern DSP engines using conventional serial port connections and an extra enable control line. Both serial input and output data use an accompa- nying frame synchronization signal which is active high one clock cycle before the start of the 16-bit word or during the last bit of the previous word if transmission is continuous. The serial clock (SCLK) is an output from the codec and is used to define the serial transfer rate to the DSP’s Tx and Rx ports. Two primary configurations can be used: the first is shown in Figure 13, where the DSP’s Tx data, Tx frame sync, Rx data and Rx frame sync are connected to the codec’s SDI, SDIFS, SDO and SDOFS, respectively. This configuration, referred to as indirectly coupled or nonframe sync loop-back, has the effect of decoupling the transmission of input data from the receipt of output data. The delay between receipt of codec output data and transmission of input data for the codec is determined by the DSP’s software latency. When programming the DSP serial port for this con- figuration, it is necessary to set the Rx FS as an input and the Tx FS as an output generated by the DSP. This configuration is most useful when operating in mixed mode, as the DSP has the ability to decide how many words (either DAC or control) can be sent to the codec(s). This means that full control can be imple- mented over the device configuration as well as updating the DAC in a given sample interval. The second configuration (shown in Figure 14) has the DSP’s Tx data and Rx data con- nected to the codec’s SDI and SDO, respectively while the DSP’s Tx and Rx frame syncs are connected to the codec’s SDIFS and SDOFS. In this configuration, referred to as directly coupled or frame sync loop-back, the frame sync signals are connected together and the input data to the codec is forced to be synchronous with the output data from the codec. The DSP must be programmed so that both the Tx FS and Rx FS are inputs as the codec SDOFS will be input to both. This configura- tion guarantees that input and output events occur simultaneously and is the simplest configuration for operation in normal Data Mode. Note that when programming the DSP in this configura- tion it is advisable to preload the Tx register with the first control word to be sent before the codec is taken out of reset. This ensures that this word will be transmitted to coincide with the first output word from the device(s). SDIFS SDI SCLK SDO SDOFS TFS DT SCLK DR RFS ADSP-218x DSP AD73311L CODEC Figure 13. Indirectly Coupled or Nonframe Sync Loop- Back Configuration Cascade Operation The AD73311L has been designed to support up to eight codecs in a cascade connected to a single serial port (see Figure 37). The SPORT interface protocol has been designed so that device addressing is built into the packet of information sent to the device. This allows the cascade to be formed with no extra hardware overhead for control signals or addressing. A cascade can be formed in either of the two modes previously discussed. There may be some restrictions in cascade operation due to the number of devices configured in the cascade and the serial clock rate chosen. Table XVII details the requirements for SCLK rate for cascade lengths from 1 to 8 devices. This assumes a directly coupled frame sync arrangement as shown in Figure 13. Table XVII. Cascade Options Number of Devices in Cascade SCLK 12345678 DMCLK DMCLK/2 DMCLK/4 XXXX DMCLK/8 XXXXXX SDIFS SDI SCLK SDO SDOFS TFS DT SCLK DR RFS ADSP-218x DSP AD73311L CODEC Figure 14. Directly Coupled or Frame Sync Loop- Back Configuration |
Similar Part No. - AD73311L_17 |
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Similar Description - AD73311L_17 |
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