ZL40813/14/18

Data Sheet

2

Zarlink Semiconductor Inc.

Figure 2 - Pin Connections - Top View

1.0

Application Configuration

Figure 3 shows a recommended application configuration. This example shows the devices set up for single-ended

input and differential output operation.

Figure 3 - Recommended circuit configuration.

The above circuit diagram shows some components in dotted lines. These are optional in many applications.

1. C1 (10 µF) and C2 (10 nF) power supply decoupling capacitors may be available on the board already.

2. R2 (100 Ohm) and C8 (10 nF) can be included if further power supply decoupling is required for the first stage

biasing circuit. This may optimise the noise and jitter performance. The values are suggestions and may have

to be modified if the existing supplies are particularly noisy.

3. R1 (50 Ohm), in series with C5 (100 pF), may reduce feedthrough of the input signal to the output.

Vcc INPUT

INPUT

INPUT B

GND

Vcc OUTPUT

OUTPUT

OUTPUT B

GND

1

2

3

4

5

6

7

8

SOIC (N) E-Pad

1

2

3

4

8

7

6

5

R2:100 Ohm

R1:50 Ohm

C1:10uF

C2:10nF

C3:100pF

C8:10nF

C4:100pF

C5:100pF

C6:100pF

C7:100pF

RL:50 Ohm