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STK12C68-5K55M Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part No. STK12C68-5K55M
Description  CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM
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STK12C68-M
4-57
Note e:
These parameters guaranteed but not tested.
Note n:
HSB is an I/O that has a weak internal pullup; it is basically an open drain output. It is meant to allow up to 32 STK12C68-Ms to be ganged together for
simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68-M HSB pins.
Note o:
A RECALL cycle is initiated automatically at power up when V
CC exceeds VSWITCH. tRECALL is measured from the point at which VCC exceeds 4.5V.
22
tRECALL
RECALL Cycle Duration
20
µs
Note o
23
tSTORE
tHLHH
STORE Cycle Duration
10
ms
VCC ≥ 4.5V
24
tDELAY
tHLQZ
HSB Low to Inhibit On
1
µs
25
t
RECOVER
t
HHQX
HSB High to Inhibit Off
300
ns
Note e
26
t
ASSERT
t
HLHX
External
STORE Pulse Width
250
ns
Note e
VSWITCH
Low Voltage Trigger Level
4.0
4.5
V
IHSB_OL
HSB Output Low Current
3
mA
HSB = VOL, Note e, n
IHSB_OH
HSB Output High Current
5
60
µA
HSB = VIL, Note e, n
NONVOLATILE MEMORY OPERATION
MODE SELECTION
H
X
H
X
Not Selected
Output High Z
Standby
L
H
H
X
Read SRAM
Output Data
Active
l
L
L
H
X
Write SRAM
Input Data
Active
L
H
H
0000
Read SRAM
Output Data
Active
k,l
1555
Read SRAM
Output Data
k,l
0AAA
Read SRAM
Output Data
k,l
1FFF
Read SRAM
Output Data
k,l
10F0
Read SRAM
Output Data
k,l
0F0F
Nonvolatile
STORE
Output High Z
k
L
H
H
0000
Read SRAM
Output Data
Active
k,l
1555
Read SRAM
Output Data
k,l
0AAA
Read SRAM
Output Data
k,l
1FFF
Read SRAM
Output Data
k,l
10F0
Read SRAM
Output Data
k,l
0F0E
Nonvolatile
RECALL
Output High Z
k
XX
L
X
STORE/Inhibit
Output High Z
ICC /Standby
m
E
W
HSB
A12 - A0(hex)
MODE
I/O
POWER
NOTES
Note k: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a
STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0,
0F0E) for a
RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details.
Note l:
I/O state assumes that G
≤ V
IL. Activation of nonvolatile cycles does not depend on the state of G.
Note m: HSB initiated
STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any) completes, the
part will go into standby mode inhibiting all operation until HSB rises.
HARDWARE
STORE /RECALL
SYMBOLS
NO.
PARAMETER
MIN
MAX
UNITS
NOTES
2
HSB
W
RECALL
STORE
SRAM
Inhibit
Software STORE
HSB Initiated STORE
Power Down STORE
Brown Out RECALL
Power Up RECALL
VSWITCH
VCAP
24
tDELAY
26
tASSERT
22
tRECALL
24
tDELAY
25
tRECOVER
23
tSTORE
23
tSTORE
23
tSTORE
HARDWARE
STORE /RECALL




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