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NM93CS66EM8 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # NM93CS66EM8
Description  (MICROWIRETM Bus Interface) 256-/1024-/2048-/4096-Bit Serial EEPROM with Data Protect and Sequential Read
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

NM93CS66EM8 Datasheet(HTML) 4 Page - National Semiconductor (TI)

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DC and AC Electrical Characteristics VCC e 45V to 55V unless otherwise specified (Continued)
Symbol
Parameter
Part Number
Conditions
Min
Max
Units
tPEH
PE Hold Time
NM93CS06 – NM93CS66
250
NM93CS06E – NM93CS66E
250
ns
NM93CS06M – NM93CS66M
500
tPREH
PRE Hold Time
50
ns
tDIH
DI Hold Time
20
ns
tPD1
Output Delay to ‘‘1’’
NM93CS06 – NM93CS66
500
NM93CS06E – NM93CS66E
500
ns
NM93CS06M – NM93CS66M
1000
tPD0
Output Delay to ‘‘0’’
NM93CS06 – NM93CS66
500
NM93CS06E – NM93CS66E
500
ns
NM93CS06M – NM93CS66M
1000
tSV
CS to Status Valid
NM93CS06 – NM93CS66
500
NM93CS06E – NM93CS66E
500
ns
NM93CS06M – NM93CS66M
1000
tDF
CS to DO in
NM93CS06 – NM93CS66
CS e VIL
100
TRI-STATE
NM93CS06E – NM93CS66E
100
ns
NM93CS06M – NM93CS66M
200
tWP
Write Cycle Time
10
ms
Capacitance (Note 3)
TA e 25 C f e 1 MHz
Symbol
Test
Typ
Max
Units
COUT
Output Capacitance
5
pF
CIN
Input Capacitance
5
pF
Note 1
Stress ratings above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device This is a stress rating only and
operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
Note 2
CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another
opcode cycle (this is shown in the opcode diagrams in the following pages)
Note 3
This parameter is periodically sampled and not 100% tested
Note 4
Typical leakage values are in the 20 nA range
Note 5
The shortest allowable SK clock period e 1fSK (as shown under the fSK parameter) Maximum SK clock speed (minimum SK period) is determined by the
interaction of several AC parameters stated in the datasheet Within this SK period both tSKH and tSKL limits must be observed Therefore it is not allowable to set
1fSK e tSKH (minimum) a tSKL (minimum) for shorter SK cycle time operation
AC Test Conditions
VCC Range
VIL VIH
VIL VIH
VOL VOH
IOL IOH
Input Levels
Timing Level
Timing Level
45V s VCC
b
21 mA
04 mA
s
55V
04V24V
10V20V
04V24V
(TTL Levels)
Output Load 1 TTL Gate (CL e 100 pF)
4


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