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M24C01-WBN6TG Datasheet(PDF) 9 Page - STMicroelectronics |
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M24C01-WBN6TG Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 29 page 9/29 M24C16, M24C08, M24C04, M24C02, M24C01 condition until the end of the address byte), the de- vice replies to the data bytes with NoAck, as shown in Figure 6., and the locations are not mod- ified. After each byte is transferred, the internal byte address counter (the 4 least significant ad- dress bits only) is incremented. The transfer is ter- minated by the bus master generating a Stop condition. Figure 7. Write Mode Sequences with WC=0 (data write enabled) BYTE WRITE DEV SEL BYTE ADDR DATA IN WC PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2 WC DATA IN 3 AI02804B PAGE WRITE (cont'd) WC (cont'd) DATA IN N ACK R/W ACK ACK ACK ACK ACK ACK R/W ACK ACK |
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