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COP8782CJ Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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COP8782CJ Datasheet(HTML) 3 Page - National Semiconductor (TI) |
3 / 28 page COP8780CCOP8781CCOP8782C Absolute Maximum Ratings If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications Supply Voltage (VCC)7V Programming Voltage VPP (RESET pin) and ME (pin G6) 134V Voltage at any Pin b 03V to VCC a 03V Total Current into VCC Pin (Source) 50 mA Total Current out of GND Pin (Sink) 60 mA Storage Temperature Range b 65 Cto a150 C Note Absolute maximum ratings indicate limits beyond which damage to the device may occur DC and AC electri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings DC Electrical Characteristics COP87XXC b40 C s TA s a85 C unless otherwise specified Parameter Condition Min Typ Max Units Operating Voltage 45 60 V Power Supply Ripple (Note 1) Peak to Peak 01 VCC V Supply Current CKI e 10 MHz (Note 2) VCC e 6V tc e 1 ms21 mA HALT Current (Note 3) VCC e 6V CKI e 0 MHz 10 m A Input Levels RESET CKI Logic High 09 VCC V Logic Low 01 VCC V All Other Inputs Logic High 07 VCC V Logic Low 02 VCC V Hi-Z Input Leakage VCC e 60V b 2 a 2 m A Input Pullup Current VCC e 60V VIN e 0V b 40 b 250 m A G Port Input Hysteresis (Note 6) 005 VCC V Output Current Levels D Outputs Source VCC e 45V VOH e 38V b 04 mA Sink VCC e 45V VOL e 10V 10 mA All Others Source (Weak Pull-Up) VCC e 45V VOH e 32V b 10 b 110 m A Source (Push-Pull Mode) VCC e 45V VOH e 38V b 04 mA Sink (Push-Pull Mode) VCC e 45V VOL e 04V 16 mA TRI-STATE Leakage b 20 a 20 m A Allowable SinkSource Current per Pin D Outputs (Sink) 15 mA All Others 3mA Maximum Input Current (Notes 4 6) Room Temp g 200 mA without Latchup (Room Temp) RAM Retention Voltage Vr 20 V (Note 5) Input Capacitance (Note 6) 7 pF Load Capacitance on D2 (Note 6) 1000 pF Note 1 Rate of voltage change must be less than 05Vms Note 2 Supply current is measured after running 2000 cycles with a square wave CKI input CKO open inputs at rails and outputs open Note 3 The HALT mode will stop CKI from oscillating in the RC and the crystal configurations Halt test conditions All Inputs tied to VCC L C and G port IO’s configured as outputs and programmed low D outputs programmed low the window for UV erasable packages is completely covered with an opaque cover to prevent light from falling onto the die during HALT mode test Parameter refers to HALT mode entered via setting bit 7 of the G Port data register Note 4 Pins G6 and RESET are designed with a high voltage input network for factory testing These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC) The effective resistance to VCC is 750X (typ) These two pins will not latch up The voltage at the pins must be limited to less than 14V Note 5 To maintain RAM integrity the voltage must not be dropped or raised instantaneously Note 6 Parameter characterized but not tested http www nationalcom 3 |
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