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CS62180 Datasheet(PDF) 12 Page - Cirrus Logic |
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CS62180 Datasheet(HTML) 12 Page - Cirrus Logic |
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12 / 50 page  TRANSMITTER The transmit sides of the CS62180B have three types of inputs, the clock, sync, and data inputs. Control is handled through the serial port in host mode, and through the mode control pins in hardware mode (see the last section for a description of hardware mode op- eration). Input Data None of the data inputs are buffered, so the data at each input must be available at the appropriate time for the CS62180B to multiplex into the output stream. All inputs are sampled on the falling edge of TCLK. The delay from input to output is 10 TCLK cycles. NRZ data for DS0 channels is input on TSER. Framing bits (FT or FPS bits) and CRC data may either be generated internally or supplied by the host system. If this data is to be externally sup- plied, it must be inserted into the DS0 input stream at the appropriate frames and input via TSER. S-bits may be generated internally, or externally provided via TLINK. FDL bits are always pro- vided externally on TLINK. Bit-ro bbe d signaling, when enabled, is always sampled at TABCD. The CS62180B muxes in data from these 3 sources (TSER, TLINK, and TABCD) automatically depending on the trans- mitter configuration. Output Data The completed T1 data stream, ready for line transmission, is output on TPOS/TNEG. For op- eration with a line interface which is transparent to line coding, the output can be set to dual- unipolar format by clearing bit 7 of the Transmit Control Register (TCR.7). TCR.7 should be set to a "1" for operation with a line interface which provides AMI or B8ZS coding. In this configura- tion, the data will be output on TPOS in NRZ format, and TNEG will remain low. When oper- ating in hardware mode, output defaults to the dual-unipolar format. TPOS and TNEG may not be tied together, so an external OR gate is rec- ommended if NRZ output is required while in hardware mode. Frame/Multiframe Synchronization The CS62180B maintain timing for frame and multiframe alignment with internal counters driven by TCLK. The timing signals generated by those counters are output on TCHCLK, TMO, TSIGSEL, TSIGFR, and TLCLK. These counters determine when the CS62180B will insert F-bits and sample external signaling data. The frame and multiframe counters can be reset independently via TMSYNC and TFSYNC. If left to run with- out a sync pulse, the CS62180B will arbitrarily choose a framing alignment. A low to high transition of TMSYNC, occurring near the rising edge of TCLK, resets the CS62180B’s counters to mark the bit-period concurrent with the next falling edge of TCLK as the F-bit of the first frame of a new superframe. All other timing will be set to match the superframe alignment automatically. TMSYNC may be pulsed once at start-up and left low, or left running in sync with superframe timing. A low to high transition of TFSYNC, occurring near the rising edge of TCLK, resets the CS62180B’s counters to mark the bit-period concurrent with the next falling edge of TCLK as the F-bit of a new frame. If TMSYNC is used to set superframe alignment, frame alignment will also be set, and TFSYNC may be tied low. There is, of course, no harm in using both TMSYNC and TFSYNC together, as TFSYNC has no effect on multiframe alignment if it is in sync. If, however, TFSYNC is used out of sync with TMSYNC, the superframe align- CS62180B 12 DS225PP2 |
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