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CS62180 Datasheet(PDF) 3 Page - Cirrus Logic

Part No. CS62180
Description  T1 FRAMER
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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 3 page
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SCLK
SDO
MSB
High-Z
High-Z
CS
CDZ
t
CDV
t
CDH2
t
Serial Port Read Timing
13. Serial port write must precede a port read to provide address information.
14. SDO will go High-Z: 1) if CS returns high at anytime; 2) after outputing MSB.
SCLK
SDI
LSB
LSB
MSB
Control Byte
Data Byte
DC
t
CC
t
CH
t
CDH1
t
CL
t
CDH1
t
CCH
t
CWH
t
CS
Serial Port Write Timing
11. In the CS62180B, data is latched on the rising edge of SCLK.
12. Shaded regions indicate
don’t care states.
SWITCHING CHARACTERISTICS - SERIAL PORT
(TA = -40 to 85
°C; VDD = 5V ± 10%; VIH = 2.0V; VIL = 0.8V; Maximum input rise & fall times of 10 ns)
Parameter
Symbol
Min
Typ
Max
Units
SDI to SCLK Setup
tDC
50
-
-
ns
SCLK to SDI Hold
tCDH1
50
-
-
ns
SCLK Low Time
tCL
250
-
-
ns
SCLK High Time
tCH
250
-
-
ns
SCLK Rise & Fall Times
(Note 9)
tR, tF
-
-
500
ns
CS to SCLK Set up
tCC
50
-
-
ns
SCLK to CS Hold
tCCH
50
-
-
ns
CS Inactive Time
tCWH
250
-
-
ns
SCLK to SDO Valid
(Note 9)
tCDV
-
-
200
ns
SCLK Rising to MSB of SDO Hold
(Note 10)
tCDH2
25
-
-
ns
CS to SDO High-Z
tCDZ
-
-
75
ns
Notes: 9. Output load capacitance = 100 pF.
10. SDO goes High-Z after rising edge of SCLK for MSB, regardless of the state of CS.
CS62180B
DS225PP2
3




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