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ADS7823E2K5 Datasheet(PDF) 10 Page - Burr-Brown (TI) |
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ADS7823E2K5 Datasheet(HTML) 10 Page - Burr-Brown (TI) |
10 / 15 page ADS7823 10 SBAS180B MSB 654321 LSB 0 0 0 XXXXX MSB 654321 LSB 10010 A1 A0 R/W ADDRESS BYTE The address byte is the first byte received following the START condition from the master device. The first five bits (MSBs) of the slave address are factory pre-set to 10010. The next two bits of the address byte are the device select bits, A1 and A0. Input pins (A1-A0) on the ADS7823 deter- mine these two bits of the device address for a particular ADS7823. A maximum of four devices with the same pre-set code can therefore be connected on the same bus at one time. The A1-A0 Address Inputs can be connected to VDD or digital ground. The device address is set by the state of these pins upon power-up of the ADS7823. The last bit of the address byte (R/W) defines the operation to be performed. When set to a “1” a read operation is selected; when set to a “0” a write operation is selected. Following the START condition the ADS7823 monitors the SDA bus, checking the device type identifier being transmit- ted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line. The ADS7823 operating mode is determined by a command byte. The ADS7823 command byte simply consists of three zeros in the most significant bits, while the remaining 5 bits are don’t cares. INITIATING CONVERSION Provided the master has write-addressed it, the ADS7823 turns on the A/D converter section and begins conversions when it receives bit 5 of the command byte shown in the Command Byte. If the command byte is correct, the ADS7823 will return an ACK condition. The converter will ignore any wrong command byte (that is, setting any of the top three MSBs to 1), remain in the A/D converter power-down mode, and reset the internal 4-word stack. The ADS7823 will ignore a second valid command byte if two valid commands are issued consecutively. The ADS7823 will respond with a not-acknowledge, and will go to the A/D con- verter power-down mode after the responded not-acknowledge. COMMAND BYTE FIGURE 3. Typical Read Sequence in F/S Mode. NOTES: (A) Failure for master to send read-addressing byte—setting R/W flag to “1”—will result in internal clock remaining ON, increasing power consumption. (B) Use repeated START to secure bus operation and loop back to the stage of write-addressing for next conversion. Sr 1 0 0 1 0 A1 A0 R A 000 0 D11 D10 D9 D8 AD7 D6 . . .D1 D0 NP SA1 1 001 0 A0 W A0 0 0 X X X X X A ADC Power-Down Mode ADC Wake-Up Mode Write-Addressing Byte Command Byte (See Note B) Read-AddressingByte (see Note A) Max. 4 × [2×(8 bits + ack/not-ack)] From master to slave From slave to master ADC Power-Down Mode A = acknowledge (SDA Low) N = not-acknowledge (SDA High) S = START Condition P = STOP Condition Sr = repeated START Condition W = 0 (WRITE) R = 1 (READ) |
Similar Part No. - ADS7823E2K5 |
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Similar Description - ADS7823E2K5 |
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