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HB28E016MM2 Datasheet(PDF) 3 Page - Hitachi Semiconductor |
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HB28E016MM2 Datasheet(HTML) 3 Page - Hitachi Semiconductor |
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3 / 88 page  HB28E016/D032/D064/B128MM2 3 Block Diagram 12 34 VPP Generator 56 7 Internal clock Interface CID[127:0] OCR[31:0] Flash control Core control CSD[127:0] RCA[15:0] VCC CS CMD/DI DAT/DO CLK/SCLK Interface driver Memory core All units in these Hitachi MultiMediaCards are clocked by an internal clock generator. The Interface driver unit synchronizes the DAT and CMD signals from external CLK to the internal used clock signal. The card is controlled by the three line MultiMediaCard interface containing the signals: CMD, CLK, DAT (refer to Chapter “Interfaces”). For the identification of the MultiMediaCard in a stack of MultiMediaCards, a card identification register (CID) and a relative card address register (RCA) is foreseen. An additional register contains different types of operation parameters. This register is called card specific data register (CSD). The communication using the MultiMediaCard lines to access either the memory field or the registers is defined by the MultiMediaCard standard (refer to Chapter “Communication”). The card has its own power on detection unit. No additional master reset signal is required to setup the card after power on. It is protected against short circuit during insertion and removal while the MultiMediaCard system is powered up (refer to Chapter “Power Supply”). No external programming voltage supply is required. The programming voltage is generated on card. These Hitachi MultiMediaCards support a second interface operation mode the SPI interface mode. The SPI mode is activated if the CS signal is asserted (negative) during the reception of the reset command (CMD0) (refer to Chapter “SPI Communication”). |
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