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IDT79R4700-175-GH Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT79R4700-175-GH Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 25 page  6 of 25 April 10, 2001 IDT79R4700 Because the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, further increasing performance by allowing these two operations to occur simul- taneously. The tag holds a 24-bit physical address and valid bit and is parity protected. The instruction cache is 64-bits wide and can be refilled or accessed in a single processor cycle. For a peak instruction bandwidth of 800MB/ sec at 200MHz, instruction fetches require only 32 bits per cycle. To reduce power dissipation, sequential accesses take advantage of the 64-bit fetch. To minimize the cache miss penalty, cache miss refill writes use 64 bits-per-cycle, and to maximize cache performance, the line size is eight instructions (32 bytes). Data Cache Data Cache Data Cache Data Cache For fast, single cycle data access, the RC4700 includes a 16KB on- chip data cache that is two-way set associative with a fixed 32-byte (eight words) line size. The data cache is protected with byte parity and its tag is protected with a single parity bit. It is virtually indexed and physically tagged to allow simultaneous address translation and data cache access The normal write policy is writeback, which means that a store to a cache line does not immediately cause memory to be updated. This increases system performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. Software can however select write- through on a per-page basis when it is appropriate, such as for frame buffers. Associated with the data cache is the store buffer. When the RC4700 executes a Store instruction, this single-entry buffer gets written with the store data while the tag comparison is performed. If the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). The store buffer allows the R4700 to execute a store instruction every processor cycle and to perform back-to-back stores without penalty. The data cache can provide 8 bytes each clock cycle, for a peak bandwidth of 1.6 GB/sec. Write Buffer Write Buffer Write Buffer Write Buffer Writes to external memory—whether they are cache miss write- backs, stores to uncached or write-through addresses—use the on-chip write buffer. The write buffer holds a maximum of four 64-bit address and 64-bit data pairs. The entire buffer is used for a data cache writeback and allows the processor to proceed in parallel with memory updates. System Interface System Interface System Interface System Interface The RC4700 supports a 64-bit system interface. This interface oper- ates from two clocks—TClock[1:0] and RClock[1:0]—provided by the RC4700, at some division of the internal clock. The system interface consists of a 64-bit Address/Data bus with eight check bits and a 9-bit command bus protected with parity. In addi- tion, there are eight handshake signals and six interrupt inputs. The interface has a simple timing specification and is capable of transferring data between the processor and memory at a peak rate of 500MB/sec with a 67MHz bus. System Address/Data Bus System Address/Data Bus System Address/Data Bus System Address/Data Bus The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RC4700 and the rest of the system. It is protected with an 8-bit parity check bus, SysADC. The system interface is configurable to allow easier interfacing to memory and I/O systems of varying frequencies. The data rate and the bus frequency at which the RC4700 transmits data to the system inter- face are programmable via boot time mode control bits. Also, the rate at which the processor receives data is fully controlled by the external device. Therefore, either a low cost interface requiring no read or write buffering or a faster, high performance interface can be designed to communicate with the RC4700. Again, the system designer has the flex- ibility to make these price/performance trade-offs. System Command Bus System Command Bus System Command Bus System Command Bus The RC4700 interface has a 9-bit System Command (SysCmd) bus. The command bus indicates whether the SysAD bus carries an address or data. If the SysAD carries an address, then the SysCmd bus also indicates what type of transaction is to take place (for example, a read or write). If the SysAD carries data, then the SysCmd bus also gives information about the data (for example, this is the last data word trans- mitted, or the cache state of this data line is clean exclusive). The SysCmd bus is bidirectional to support both processor requests and external requests to the RC4700. Processor requests are initiated by the RC4700 and responded to by an external device. External requests are issued by an external device and require the RC4700 to respond. The RC4700 supports one to eight byte and block transfers on the SysAD bus. In the case of a sub-doubleword transfer, the low-order three address bits give the byte address of the transfer, and the SysCmd bus indicates the number of bytes being transferred. Handshake Signals Handshake Signals Handshake Signals Handshake Signals There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy* are used by an external device to indicate to the RC4700 whether it can accept a new read or write transaction. The RC4700 samples these signals before deasserting the address on read and write requests. ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses between the processor and an external device. When an external device needs to control the interface, it asserts ExtRqst*. The RC4700 responds by asserting Release* to release the system interface to slave state. |
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