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IDT72T40118L5BB Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72T40118L5BB Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 52 page 9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 Symbol Rating Commercial Unit VTERM TerminalVoltage –0.5 to +3.6(2) V with respect to GND TSTG StorageTemperature –55 to +125 °C IOUT DC Output Current –50 to +50 mA DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 2.5V ± 0.125V, TA = 0 °C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 2.375 2.5 2.625 V GND Supply Voltage 0 0 0 V VIH Input High Voltage LVTTL 1.7 — 3.45 V eHSTL VREF+0.2 — — V HSTL VREF+0.2 — — V VIL Input Low Voltage LVTTL -0.3 — 0.7 V eHSTL — — VREF-0.2 V HSTL — — VREF-0.2 V VREF VoltageReferenceInput eHSTL 0.8 0.9 1.0 V (HSTL only) HSTL 0.68 0.75 0.9 V TA OperatingTemperatureCommercial 0 — 70 °C TA OperatingTemperatureIndustrial -40 — 85 °C Symbol Parameter Min. Max. Unit ILI InputLeakageCurrent –10 10 µA ILO OutputLeakageCurrent –10 10 µA VOH(5) Output Logic “1” Voltage, IOH = –8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) VDDQ -0.4 — V IOH = –8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) VDDQ -0.4 — V IOH = –8 mA @VDDQ = 1.5V ± 0.1V (HSTL) VDDQ -0.4 — V VOL Output Logic “0” Voltage, IOL = 8 mA @VDDQ = 2.5V ± 0.125V (LVTTL) — 0.4V V IOL = 8 mA @VDDQ = 1.8V ± 0.1V (eHSTL) — 0.4V V IOL = 8 mA @VDDQ = 1.5V ± 0.1V (HSTL) — 0.4V V ICC1(1,2) Active VCC Current (VCC = 2.5V) I/O = LVTTL — 20 mA I/O = HSTL — 60 mA I/O = eHSTL — 60 mA ICC2(1) Standby VCC Current (VCC = 2.5V) I/O = LVTTL — 10 mA I/O = HSTL — 50 mA I/O = eHSTL — 50 mA ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Compliant with JEDEC JESD8-5. VCC terminal only. Symbol Parameter (1) Conditions Max. Unit CIN(2,3) Input VIN = 0V 10(3) pF Capacitance COUT(1,2) Output VOUT = 0V 10 pF Capacitance CAPACITANCE (TA= +25 °C, f = 1.0MHz) NOTES: 1. With output deselected, ( OE ≥ VIH). 2. Characterized values, not currently tested. 3. CIN for Vref is 20pF. NOTES: 1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH. 2. Typical ICC1 calculation: for LVTTL I/O ICC1 (mA) = 0.6mA x fs, fs = WCLK frequency = RCLK frequency (in MHz) for HSTL or eHSTL I/O ICC1 (mA) = 38mA + (0.7mA x fs), fs = WCLK frequency = RCLK frequency (in MHz) 3. Typical IDDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.15mA x fs With Data Outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x 2N)/2000 fs = WCLK frequency = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, N = Number of outputs switching. tA = 25°C, CL = capacitive load (pf) 4. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)]. 5. Outputs are not 3.3V tolerant. NOTE: 1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation. |
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