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IDT72T40108L10BB Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT72T40108L10BB Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 52 page 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 PIN DESCRIPTION BM(1) Bus-Matching LVTTL During Master Reset, this pin along with IW and OW selects the bus sizes for both write and read (K2) INPUT ports. D0-D39 Data Inputs HSTL-LVTTL Data inputs for a 40-, 20-, or 10-bit bus. When in 20- or 10- bit mode, the unused input pins are in a don’t (See Pin No. INPUT care state. The data bus is sampled on both rising and falling edges of WCLK when WENisenabledand table for details) DDR Mode is enabled or on the rising edges of WCLK only in SDR Mode. EF/OR Empty Flag/ HSTL-LVTTL In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory (M14) Output Ready OUTPUT is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. ERCLK Echo Read HSTL-LVTTL Read Clock Echo output, must be equal to or faster than the Qn data outputs. (L16) Clock OUTPUT EREN Echo Read HSTL-LVTTL Read Enable Echo output, used in conjunction with ERCLK. (K16) Enable OUTPUT FF/IR Full Flag/ HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is (H3) Input Ready OUTPUT empty. In FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. FSEL0(1) Flag Select Bit 0 LVTTL DuringMasterReset,thisinputalongwithFSEL1willselectthedefaultoffsetvaluesfortheprogrammable (J3) INPUT flags PAE and PAF. There are four possible settings available. FSEL1(1) Flag Select Bit 1 LVTTL During Master Reset, this input along with FSEL0 will select the default offset values for the programmable (J2) INPUT flags PAE and PAF. There are four possible settings available. FWFT First Word Fall LVTTL During Master reset, selects First Word Fall Through or IDT Standard mode. FWFT is not available in (G2) Through INPUT DDR mode. In SDR mode, the first word will always fall through on the rising edge. HSTL(1) HSTL Select LVTTL This input pin is used to select HSTL or 2.5V LVTTL device operation. If HSTL inputs are required, this (B7) INPUT input must be tied HIGH, otherwise it must be tied LOW and cannot toggle during operation. IW(1) InputWidth LVTTL During Master Reset, this pin along with OW and BM, selects the bus width of the read and write port. (K1) INPUT MARK Mark Read HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit (E14) Pointer for INPUT operation will reset the read pointer to this position. There is an unlimited number to times to set the mark Retransmit location, but only the most recent location marked will be acknowledged. MRS Master Reset HSTL-LVTTL MRSinitializesthereadandwritepointerstozeroandsetstheoutputregisterstoallzeros.DuringMaster (J1) INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, and programmableflagdefaultsettings. OE OutputEnable HSTL-LVTTL WhenHIGH,dataoutputsQ0-Q39areinhighimpedance.WhenLOW,thedataoutputsQ0-Q39areenabled. (G15) INPUT No other outputs are affected by OE. OW(1) OutputWidth LVTTL During Master Reset, this pin along with IW and BM, selects the bus width of the read and write port. (L3) INPUT PAE Programmable HSTL-LVTTL PAEgoes HIGH if the number of words in the FIFO memory is greater than or equal to offset n, which is (L15) Almost-Empty OUTPUT storedintheEmptyOffsetregister. PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthan Flag offsetn. PAF Programmable HSTL-LVTTL PAFgoesHIGHifthenumberoffreelocationsintheFIFOmemoryismorethanoffsetm,whichisstored (G3) Almost-FullFlag OUTPUT in the Full Offset register. PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthan or equal to m. PRS PartialReset HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregisterstoallzeros.DuringPartial (K3) INPUT Reset, the existing mode (IDT standard or FWFT) and programmable flag settings are not affected. Q0-Q39 DataOutputs HSTL-LVTTL Data outputs for a 40-, 20-, or 10-bit bus. When in 20- or 10- bit mode, the unused output pins should not (See Pin No. OUTPUT be connected. The output data is clocked on both rising and falling edges of RCLK when RENisenabled table for details) and DDR Mode is enabled or on the rising edges of RCLK only in SDR Mode. RCLK Read Clock HSTL-LVTTL Inputclockwhenusedinconjunctionwith RENforreadingdatafromtheFIFOmemoryandoutputregister. (G16) INPUT Symbol & Name I/O TYPE Description Pin No. |
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