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IDT72T4088L5BBI Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT72T4088L5BBI Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 52 page 4 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72T4088/98/108/118 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 40-BIT CONFIGURATION 16,384 x 40, 32,768 x 40, 65,536 x 40 and 131,072 x 40 DESCRIPTION (CONTINUED) PAEandPAFflagscanbeprogrammedindependentlytoswitchatanypoint inmemory.Programmableoffsetsmarkthelocationwithintheinternalmemory that activates the PAEandPAFflagsandcanonlybeprogrammedserially.To program the offsets, set SENactiveanddatacanbeloadedviatheSerialInput (SI) pin at the rising edge of SCLK. To read out the offset registers serially, set SRENactiveanddatacanbereadoutviatheSerialOutput(SO)pinattherising edge of SCLK. Four default offset settings are also provided, so that PAEcan be marked at a predefined number of locations from the empty boundary and the PAFthresholdcanalsobemarkedatsimilarpredefinedvaluesfromthefull boundary. The default offset values are set during Master Reset by the state of the FSEL0 and FSEL1 pins. During Master Reset ( MRS),thefollowingeventsoccur:thereadandwrite pointers are set to the first location of the internal FIFO memory, the FWFT pin selects IDT Standard mode or FWFT mode, the bus width configuration of the readandwriteportisdeterminedbythestateofIWandOW,andthedefaultoffset values for the programmable flags are set. The Partial Reset ( PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode and the values stored in the programmable offset registers before Partial Reset remain unchanged. The flagsareupdatedaccordingtothetimingmodeandoffsetsineffect. PRSisuseful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. The timing of the PAE and PAF flags are synchronous to RCLK and WCLK, respectively. The PAE flag is asserted upon the rising edge of RCLK only and not WCLK. Similarly the PAF is asserted and updated on the rising edge of WCLK only and not RCLK. ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol inputs, MARK and RT(Retransmit).IftheMARKinputisenabledwithrespect to the RCLK, the memory location being read at the point will be marked. Any subsequent retransmit operation (when RT goes LOW), will reset the read pointer to this “marked” location. The device can be configured with different input and output bus widths as previously stated. These rates are: x40 to x40, x40 to x20,x40 to x10, x20 to x40, and x10 to x40. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply currentconsumptionisminimized.Initiatinganyoperation(byactivatingcontrol inputs) will immediately take the device out of the power down state. A JTAG test port is provided, here the FIFO has fully functional boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and Boundary Scan Architecture. The Double Data Rate FIFO has the capability of operating in either LVTTL or HSTL mode. HSTL mode can be selected by enabling the HSTL pin. Both input and output ports will operate in either HSTL or LVTTL mode, but cannot be selected independent of one another. The IDT72T4088/72T4098/72T40108/72T40118 are fabricated using IDT’s high-speed submicron CMOS technology. |
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