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IDT79RV4700-150DF Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT79RV4700-150DF Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 25 page  5 of 25 April 10, 2001 IDT79R4700 The RC4700 processor also supports a supervisor mode in which the virtual address space is 256.5GB (2.5GB in 32-bit address mode), divided into three regions that are based on the high-order bits of the virtual address. If the RC4700 is configured for 64-bit virtual addressing, the virtual address space layout is an upwardly compatible extension of the 32-bit virtual address space layout. Figure 4 on page 5 shows the address space layout for the 32-bit virtual address operation. Memory Management Unit (MMU) Memory Management Unit (MMU) Memory Management Unit (MMU) Memory Management Unit (MMU) The Memory management unit controls the virtual memory system page mapping. It consists of an instruction address translation buffer (the ITLB), a data address translation buffer (the DTLB), a Joint TLB (the JTLB), and co-processor registers used for the virtual memory mapping sub-system. Instruction TLB (ITLB) Instruction TLB (ITLB) Instruction TLB (ITLB) Instruction TLB (ITLB) The RC4700 also incorporates a two-entry instruction TLB. Each entry maps a 4KB page. The instruction TLB improves performance by allowing instruction address translation to occur in parallel with data address translation. When a miss occurs on an instruction address translation, the least-recently used ITLB entry is filled from the JTLB. The operation of the ITLB is invisible to the user. Data TLB (DTLB) Data TLB (DTLB) Data TLB (DTLB) Data TLB (DTLB) The RC4700 also incorporates a four-entry data TLB. Each entry maps a 4KB page. The data TLB improves performance by allowing data address translation to occur in parallel with instruction address translation. When a miss occurs on a data address translation, the DTLB is filled from the JTLB. The DTLB refill is pseudo-LRU: the least recently used entry of the least recently used half is filled. The operation of the DTLB is invisible to the user. Joint TLB (JTLB) Joint TLB (JTLB) Joint TLB (JTLB) Joint TLB (JTLB) For fast virtual-to-physical address decoding, the RC4700 uses a large, fully associative TLB that maps 96 virtual pages to their corre- sponding physical addresses. The TLB is organized as 48 pairs of even- odd entries and maps a virtual address and address space identifier into the large, 64GB physical address space. Two mechanisms are provided to assist in controlling the amount of mapped space and the replacement characteristics of various memory regions. First, the page size can be configured, on a per-entry basis, to map a page size of 4KB to 16MB (in multiples of 4). A CP0 register is loaded with the page size of a mapping, and that size is entered into the TLB when a new entry is written. Thus, operating systems can provide special purpose maps; for example, a typical frame buffer can be memory mapped using only one TLB entry. The second mechanism controls the replacement algorithm, when a TLB miss occurs. The RC4700 provides a random replacement algo- rithm to select a TLB entry to be written with a new mapping; however, the processor provides a mechanism whereby a system specific number of mappings can be locked into the TLB and avoid being randomly replaced. This facilitates the design of real-time systems, by allowing deterministic access to critical software. The joint TLB also contains information to control the cache coher- ency protocol for each page. Specifically, each page has attribute bits to determine whether the coherency algorithm is uncached, non-coherent write-back, non-coherent write-through write-allocate or non-coherent write-through no write-allocate. Non-coherent write-back is typically used for both code and data on the RC4700; however, hardware-based cache coherency is not supported. Cache Memory Cache Memory Cache Memory Cache Memory To keep the RC4700’s high-performance pipeline full and operating efficiently, the RC4700 incorporates on-chip instruction and data caches that can be accessed in a single processor cycle. Each cache has its own 64-bit data path and can be accessed in parallel. Instruction Cache Instruction Cache Instruction Cache Instruction Cache The RC4700 incorporates a two-way set associative on-chip instruc- tion cache. This virtually indexed, physically tagged cache is 16KB in size and is protected with word parity. 0xFFFFFFFF 0xE0000000 Kernel virtual address space (kseg3) Mapped, 0.5GB 0xDFFFFFFF Supervisor virtual address space (sseg) Mapped, 0.5GB 0xC0000000 0xBFFFFFFF 0xA0000000 Uncached kernel physical address space (kseg1) Unmapped, 0.5GB 0x9FFFFFFF 0x80000000 Cached kernel physical address space (kseg0) Unmapped, 0.5GB 0x7FFFFFF 0x00000000 User virtual address space (useg) Mapped, 2.0GB Figure 4 Kernel Mode Virtual Addressing (32-bit Mode) |
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