Single-Supply 3V/5V, Voltage-Output, Dual,

Precision 10-Bit DACs

6

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TIMING CHARACTERISTICS—MAX5236 (FIGURES 1 AND 2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SCLK Clock Period

74

ns

SCLK Pulse Width High

30

ns

SCLK Pulse Width Low

30

ns

CS Fall to SCLK Rise Setup Time

30

ns

SCLK Rise to CS Rise Hold Time

0ns

DIN Setup Time

30

ns

DIN Hold Time

0ns

SCLK Rise to CS Fall Delay

10

ns

CS Rise to SCLK Rise Hold Time

30

ns

CS Pulse Width High

75

ns

LDAC Pulse Width Low

30

ns

CS Rise to LDAC Rise Hold Time

(Note 9)

75

ns

Note 1: Accuracy is guaranteed in the following way:

Note 2: Offset is measured at the code closest to 12mV.

Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change

DAC B to full scale and measure

DC crosstalk is the maximum

Note 7: Guaranteed by design. Not production tested.

Note 9: This timing requirement applies only to CS rising edges, which execute commands modifying the DAC input register contents.

ACCURACY GUARANTEED FROM CODE

TO CODE

3

1.250

6

1023

5

2.500

3

1023