SDRAM 64Mb H-die (x4, x8, x16)

CMOS SDRAM

Rev. 1.8 August 2004

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Notes :

DQ BUFFER OUTPUT DRIVE CHARACTERISTICS

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Notes

Output rise time

trh

Measure in linear

region : 1.2V ~ 1.8V

1.37

4.37

Volts/ns

3

Output fall time

tfh

Measure in linear

region : 1.2V ~ 1.8V

1.30

3.8

Volts/ns

3

Output rise time

trh

Measure in linear

region : 1.2V ~ 1.8V

2.8

3.9

5.6

Volts/ns

1,2

Output fall time

tfh

Measure in linear

region : 1.2V ~ 1.8V

2.0

2.9

5.0

Volts/ns

1,2

1. Rise time specification based on 0pF + 50

2. Fall time specification based on 0pF + 50

3. Measured into 50pF only, use these values to characterize to.

Notes :

Parameter

Symbol

60

70

75

Unit

Note

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS latency=3

6

1000

7

1000

7.5

1000

ns

1

CAS latency=2

101010

CLK to valid

output delay

CAS latency=3

-5-6-

5.4

ns

1,2

CAS latency=2

-

6-6-6

Output data

hold time

CAS latency=3

2.5

-

3-3-

ns

2

CAS latency=2

3

-3-3-

CLK high pulse width

2.5

-

3

-

2.5

-

ns

3

CLK low pulse width

2.5

-

3

-

2.5

-

ns

3

Input setup time

1.5

-

2

-

1.5

-

ns

3

Input hold time

1-1-

0.8

-

ns

3

CLK to output in Low-Z

1-1-1-

ns

2

CLK to output

in Hi-Z

CAS latency=3

-5-6-

5.4

ns

CAS latency=2

-

6-6-6