QL901M-6PS680C datasheet(11/37 Pages) ETC

Part #	QL901M-6PS680C

Description	QuickMIPS ESP Family

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QL901M QuickMIPS™ Data Sheet Rev B

11

•

Figure 10: RAM Module

Table 8: RAM Cell Synchronous Write Timing

Symbol

Parameter

Propagation

delay (ns)

RAM Cell Synchronous Write Timing

tSWA

WA setup time to WCLK: the amount of time the WRITE ADDRESS must be

stable before the active edge of the WRITE CLOCK

0.675

tHWA

WA hold time to WCLK: the amount of time the WRITE ADDRESS must be

stable after the active edge of the WRITE CLOCK

0

tSWD

WD setup time to WCLK: the amount of time the WRITE DATA must be stable

before the active edge of the WRITE CLOCK

0.654

tHWD

WD hold time to WCLK: the amount of time the WRITE DATA must be stable

after the active edge of the WRITE CLOCK

0

tSWE

WE setup time to WCLK: the amount of time the WRITE ENABLE must be

stable before the active edge of the WRITE CLOCK

0.623

tHWE

WE hold time to WCLK: the amount of time the WRITE ENABLE must be stable

after the active edge of the WRITE CLOCK

0

tWCRD

WCLK to RD (WA=RA): the amount of time between the active WRITE CLOCK

edge and the time when the data is available at RD

4.38

WA

WD

WE

WCLK

RE

RCLK

RA

RD

QuickRAM Module

[9:0]

[17:0]

[9:0]

[17:0]

MODE

ASYNCRD

[1:0]

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