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May 25, 2004

IDT 79RC32355

RWN

O

High Drive Read or Write. This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write

transaction. A high level indicates a read from an external device, a low level indicates a write to an external device.

OEN

O

High Drive Output Enable. This signal is asserted low when data should be driven by an external device during device read transac-

tions on the memory and peripheral bus.

BWEN[3:0]

O

High Drive SDRAM Byte Enable Mask or Memory and I/O Byte Write Enables. These signals are used as data input/output masks

during SDRAM transactions and as byte write enable signals during device controller transactions on the memory and

peripheral bus. They are active low.

BWEN[0] corresponds to byte lane MDATA[7:0].

BWEN[1] corresponds to byte lane MDATA[15:8].

BWEN[2] corresponds to byte lane MDATA[23:16].

BWEN[3] corresponds to byte lane MDATA[31:24].

SDCSN[1:0]

O

High Drive SDRAM Chip Select. These signals are used to select the SDRAM device on the memory and peripheral bus. Each bit is

asserted low during an access to the selected SDRAM.

RASN

O

High Drive SDRAM Row Address Strobe. The row address strobe asserted low during memory and peripheral bus SDRAM transac-

tions.

CASN

O

High Drive SDRAM Column Address Strobe. The column address strobe asserted low during memory and peripheral bus SDRAM

transactions.

SDWEN

O

High Drive SDRAM Write Enable. Asserted low during memory and peripheral bus SDRAM write transactions.

CKENP

O

Low Drive SDRAM Clock Enable. Asserted high during active SDRAM clock cycles.

Primary function: General Purpose I/O, GPIOP[21].

SDCLKINP

I

STI

SDRAM Clock Input. This clock input is a delayed version of SYSCLKP. SDRAM read data is sampled into the RC32355

on the rising edge of this clock.

ATM Interface

ATMINP[11:0]

I

STI

ATM PHY Inputs. These pins are the inputs for the ATM interface.

ATMIOP[1:0]

I/O

Low Drive

with STI

ATM PHY Bidirectional Signals. These pins are the bidirectional pins for the ATM interface.

ATMOUTP[9:0]

O

Low Drive ATM PHY Outputs. These pins are the outputs for the ATM interface.

TXADDR[1:0]

O

Low Drive ATM Transmit Address [1:0]. 2-bit address bus used for transmission in Utopia-2 mode.

TXADDR[0] Primary function: General purpose I/O, GPIOP[22].

TXADDR[1] Primary function: General purpose I/O, GPIOP[23].

RXADDR[1:0]

O

Low Drive ATM Receive Address [1:0]. 2-bit address bus for receiving in Utopia-2 mode.

RXADDR[0] Primary function: General purpose I/O, GPIOP[24].

RXADDR[1] Primary function: General purpose I/O, GPIOP[25].

TDM Bus

TDMDOP

O

High Drive TDM Serial Data Output. Serial data is driven by the RC32355 on this signal during an active output time slot. During inac-

tive time slots this signal is tri-stated.

Primary function: General purpose I/O, GPIOP[32].

TDMDIP

I

STI

TDM Serial Data Input. Serial data is received by the RC32355 on this signal during active input time slots.

Primary function: General purpose I/O, GPIOP[33].

TDMFP

I/O

High Drive TDM Frame Signal. A transition on this signal, the active polarity of which is programmable, delineates the start of a new

TDM bus frame. TDMFP is driven if the RC32355 is a master, and is received if it is a slave.

Primary function: General purpose I/O, GPIOP[34].

TDMCLKP

I

STI

TDM Clock. This input clock controls the rate at which data is sent and received on the TDM bus.

Primary function: General purpose I/O, GPIOP[35].

Name

Type I/O Type

Description

Table 1 Pin Descriptions (Part 2 of 8)