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79RC32355150DHI Datasheet(PDF) 2 Page - Integrated Device Technology |
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79RC32355150DHI Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 47 page  2 of 47 May 25, 2004 IDT 79RC32355 ◆ USB – Revision 1.1 compliant – USB slave device controller – Supports a 6th USB endpoint – Full speed operation at 12 Mb/s – Supports control, interrupt, bulk and isochronous endpoints – Supports USB remote wakeup – Integrated USB transceiver ◆ TDM – Serial Time Division Multiplexed (TDM) voice and data inter- face – Provides interface to telephone CODECs and DSPs – Interface to high quality audio A/Ds and D/As with external glue logic – Support 1 to 128 8-bit time slots – Compatible with Lucent CHI, GCI, Mitel ST-bus, K2 and SLD busses – Supports data rates of up to 8.192 Mb/s – Supports internal or external frame generation – Supports multiple non-contiguous active input and output time slots ◆ EJTAG – Run-time Mode provides a standard JTAG interface – Real-Time Mode provides additional pins for real-time trace information ◆ Ethernet – Full duplex support for 10 and 100 Mb/s Ethernet – IEEE 802.3u compatible Media Independent Interface (MII) with serial management interface – IEEE 802.3u auto-negotiation for automatic speed selection – Flexible address filtering modes – 64-entry hash table based multicast address filtering ◆ ATM SAR – Can be configured as one UTOPIA level 1 interface or 1 UTOPIA level 2 interface with 2 address lines (3 PHYs max) – Supports 25Mb/s and faster ATM – Supports UTOPIA data path interface operation at speeds up to 33 MHz – Supports standard 53-byte ATM cells – Performs HEC generation and checking – Cell processing discards short cells and clips long cells – 16 cells worth of buffering – UTOPIA modes: 8 cell input buffer and 8 cell output buffer – Hardware support for CRC-32 generation and checking for AAL5 – Hardware support for CRC-10 generation and checking – Virtual caching receive mechanism supports reception of any length packet without CPU intervention on up to eight simulta- neously active receive channels – Frame Mode transmit mechanism supports transmission of any length packet without CPU intervention ◆ System Features – JTAG Interface (IEEE Std. 1149.1 compatible) – 208 pin PQFP package – 2.5V core supply and 3.3V I/O supply – Up to 180 MHz pipeline frequency and up to 75 MHz bus frequency Figure 2 Example of xDSL Residential Gateway Using RC32355 SLIC Codec Echo POTS telephone RJ11 Ethernet Transceiver MII I/F DMA Channels USB TDM Timers UART Interrupt Ctl RC32300 CPU Core Data Buffers SDRAM Ctl Memory & I/O Controller ATM I/F Ethernet MAC Ethernet to PC Clock SDRAM Memory & I/O Transmission Convergence Data Pump AFE USB to PC Debug port 32-bit Data Bus |
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