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May 25, 2004

IDT 79RC32355

DMAREQN

I

STI

External DMA Device Request. The external DMA device asserts this pin low to request DMA service.

Primary function: General purpose I/O, GPIOP[18]. At reset, this pin defaults to primary function GPIOP[18].

DMADONEN

I

STI

External DMA Device Done. The external DMA device asserts this signal low to inform the RC32355 that it is done with

the current DMA transaction.

Primary function: General purpose I/O, GPIOP[19]. At reset, this pin defaults to primary function GPIOP[19].

USB

USBCLKP

I

STI

USB Clock. 48 MHz clock input used as time base for the USB interface.

USBDN

I/O

USB

USB D- Data Line. This is the negative differential USB data signal.

USBDP

I/O

USB

USB D+ Data Line. This is the positive differential USB data signal.

USBSOF

O

Low Drive USB start of frame.

Primary function: General Purpose I/O, GPIOP[20]. At reset, this pin defaults to primary function GPIOP[20].

Ethernet

MIICOLP

I

STI

MII Collision Detected. This signal is asserted by the ethernet PHY when a collision is detected.

MIICRSP

I

STI

MII Carrier Sense. This signal is asserted by the ethernet PHY when either the transmit or receive medium is not idle.

MIIMDCP

O

Low Drive MII Management Data Clock. This signal is used as a timing reference for transmission of data on the management inter-

face.

MIIMDIOP

I/O

Low Drive

with STI

MII Management Data. This bidirectional signal is used to transfer data between the station management entity and the

ethernet PHY.

MIIRXCLKP

I

STI

MII Receive Clock. This clock is a continuous clock that provides a timing reference for the reception of data.

MIIRXDP[3:0]

I

STI

MII Receive Data. This nibble wide data bus contains the data received by the ethernet PHY.

MIIRXDVP

I

STI

MII Receive Data Valid. The assertion of this signal indicates that valid receive data is in the MII receive data bus.

MIIRXERP

I

STI

MII Receive Error. The assertion of this signal indicates that an error was detected somewhere in the ethernet frame cur-

rently being sent in the MII receive data bus.

MIITXCLKP

I

STI

MII Transmit Clock. This clock is a continuous clock that provides a timing reference for the transfer of transmit data.

MIITXDP[3:0]

O

Low Drive MII Transmit Data. This nibble wide data bus contains the data to be transmitted.

MIITXENP

O

Low Drive MII Transmit Enable. The assertion of this signal indicates that data is present on the MII for transmission.

MIITXERP

O

Low Drive MII Transmit Coding Error. When this signal is asserted together with MIITXENP, the ethernet PHY will transmit symbols

which are not valid data or delimiters.

SCLP

I/O

Low Drive

with STI

Primary function: General purpose I/O, GPIOP[15]. At reset, this pin defaults to primary function GPIOP[15].

SDAP

I/O

Low Drive

with STI

Primary function: General purpose I/O, GPIOP[14]. At reset, this pin defaults to primary function GPIOP[14].

EJTAG

JTAG_TCK

I

STI

JTAG Clock. This is an input test clock, used to shift data into or out of the boundary scan logic. This signal requires an

external resistor, listed in Table 16.

JTAG_TDI

I

STI

JTAG Data Input. This is the serial data shifted into the boundary scan logic. This signal requires an external resistor,

listed in Table 16. This is also used to input EJTAG_DINTN during EJTAG/ICE mode. EJTAG_DINTN is an interrupt to

switch the PC trace mode off.

JTAG_TDO

O

Low Drive JTAG Data Output. This is the serial data shifted out from the boundary scan logic. When no data is being shifted out, this

signal is tri-stated. This signal requires an external resistor, listed in Table 16. This is also used to output the EJTAG_TPC

during EJTAG/ICE mode. EJTAG_TPC is the non-sequential program counter output.

Name

Type I/O Type

Description

Table 1 Pin Descriptions (Part 5 of 8)