M1010-01 Datasheet Rev 0.4

3 of 8

Revised 29Sep2003

Integ r ated Circuit Systems , Inc. ● Comm unications Modules ● www.i cst. com ● tel (508) 852-5400

M1010-01

Preliminar y In f o r m atio n

Integrated

Circuit

Systems, Inc.

Mfin (Frequency Input) Divider Look-Up Table (LUT)

(“Mfin”).

SEL2:0 Look-up Table (LUT)

divider values M and R to enable adjustment of loop

bandwidth and jitter tolerance.

The M1010-01 is a PLL (Phase Locked Loop) based

clock generator that generates output clocks synchro-

nized to one of two selectable input reference clocks.

An internal high "Q" SAW filter provides low jitter signal

performance and controls the output frequency of the

VCSO (Voltage Controlled SAW Oscillator).

A configurable frequency divider (labeled “Mfin Divider”)

provides the division options to accomodate various

reference clock frequencies.

In addition, configurable feedback and reference

dividers (the “M Divider” and “R Divider”) provide divider

value options to enable adjustment of loop bandwidth

and jitter tolerance.

Information”

frequency:

The Mfin feedback divider allows an input frequency to

the actual input reference clock frequencies can be:

155.52

The PLL

The PLL uses a phase detector and configurable

dividers to synchronize the output of the VCSO with

selected reference clock.

The “Mfin Divider” and “M Divider” divide the VCSO

frequency, feeding the result into the phase detector.

The selected input reference clock is divided by the “R

Divider”. The result is fed into the other input of the

phase detector.

The phase detector compares its two inputs. It then

outputs pulses to the loop filter as needed to increase or

decrease the VCSO frequency and thereby match and

lock the divider output’s frequency and phase to those

of the input reference clock.

Due to the narrow tuning range of the VCSO

(+200ppm), appropriate selection of all of the following

are required for the PLL be able to lock: VCSO center

frequency, input frequency, and divider selections.

Relationship Among Frequencies and Dividers

The VCSO center frequency must be specified at time

of order. The relationship between the VCSO (Fvcso)

frequency, the Mfin divider, the M divider, the R divider,

and the input reference frequency (Fin) is:

Clock Output

The M1010-01 provides one differential LVPECL output

available; consult factory.

FIN_SEL1:0

Mfin Value

M1010-01-155.5200

Note 1: Example with M1010-01-155.5200.

0

0

8

19.44

0

1

2

77.76

10

1

155.52

1

1

x

Test mode. Do not use.

Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT)

SEL2:0

M

R

Description

0 0 0

236

236

Various divider values to adjust bandwidth

and jitter tolerance

00 1

79

79

01 0

14

14

0 1 1

239

239

10 0

1

1

10 1

2

2

11 0

4

4

11 1

8

8

Table 4: SEL2:0 Look-up Table (LUT)

Fvcso

Fin

Mfin

×

M

R

----

×

=