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DS25C400TUT Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DS25C400TUT Datasheet(HTML) 4 Page - National Semiconductor (TI) |
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4 / 26 page  Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Continued) Symbol Parameter Conditions Min Typ (Note 2) Max Units LVCMOS DC SPECIFICATIONS — Control Pins EIA/JESD8-7 Compliant I IH High Level Input Current V IN =DVDD = 1.9 V (input and pull-low) 0.1 mA I IH High Level Input Current V IN =DVDD = 1.9 V (input with pull-high) −10 +10 µA I IL Low Level Input Current V IN = GND, DVDD = 1.9 V (input with pull-low) −10 +10 µA I IL Low Level Input Current V IN = GND, DVDD = 1.9 V (input with pull-high) −0.1 mA V OH High Level Output Voltage I OH =−2 mA DV DD −0.45 V V OL Low Level Output Voltage I OL = 2 mA 0.45 V SUPPLY CURRENT I DD Total Supply Current K28.5 pattern at 2.5 Gbps with no pre-emphasis. SSTL outputs no load termination resistors, Tx high speed serial outputs driving 100 Ω differential, no high speed Rx input data. V DDHS +VDDIO +VDDB 572 600 mA DV DD +VDDQ 130 136.5 mA P D Total Power Consumption K28.5 pattern at 2.5 Gbps with no pre-emphasis. SSTL outputs no load termination resistors, Tx high speed serial outputs driving 100 Ω differential, no high speed Rx input data. SERDES and SSTL I/O 1708 1940 mW RECOMMENDED INPUT REFERENCE CLOCK (REFCLK±) AC coupled differential signal VIDS RCLK Differential Input Voltage Figure 1 Terminated by 50 Ω parallel termination 600 1500 mV p-p V ICM Common Mode Voltage Terminated by 50 Ω Parallel Termination 1.0 V DDHS −0.5 V R REFCLK Input Termination to GND Equivalent Parallel Input Termination at REFCLK+ or REFCLK− to GND 100 Ω f REF REFCLK Frequency Range 106.25 125 MHz df REF REFCLK Frequency Variation Variation from Nominal Frequency −100 +100 ppm t REF-DC REFCLK Duty Cycle (Note 3) Between 50% of the differential voltage across REFCLK+ and REFCLK− 40 50 60 % t REF-RJ REFCLK Input Random (rms) Jitter 35 ps t REF-RJ REFCLK Input Peak-to-Peak Jitter 25 40 ps t REF-X REFCLK Transition Time Figure 1 Transition time between 20% and 80% of the differential voltage across REFCLK+ and REFCLK− 0.2 1 ns www.national.com 4 |
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