10 / 34 page  CY7C1360B CY7C1362B Document #: 38-05291 Rev. *C Page 10 of 34 ADSP 84 84 A4 B9 Input- Synchronous Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog- nized. ASDP is ignored when CE1 is deasserted HIGH. ADSC 85 85 P4 A8 Input- Synchronous Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog- nized. ZZ 64 64 T7 H11 Input- Asynchronous ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs, DQPs 58,59,62, 63,68,69, 72,73,8,9, 12,13,18, 19,22,23, 74,24 58,59,62, 63,68,69, 72,73,8,9, 12,13,18, 19,22,23, 74,24 P7,K7, G7,E7, F6,H6,L6, N6,D1, H1,L1, N1,E2, G2,K2, M2,D6, P2 J10,K10, L10,M10, D11,E11, F11,G11,J1, K1,L1,M1,D 2,E2,F2, G2,C11,N1 I/O- Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the a Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a three-state condition. VDD 15,41,65, 91 15,41,65, 91 C4,J2,J4, J6,R4 D4,D8,E4,E 8,F4,F8, G4,G8,H4, H8,J4,J8, K4,K8,L4, L8,M4,M8 Power Supply Power supply inputs to the core of the device. VSS 17,40,67, 90 17,40,67, 90 D3,D5, E5,E3,F3, F5,G5, H3,H5, K3,K5,L3, M3,M5, N3,N5, P3,P5 H2,C4,C5, C6,C7,C8, D5,D6,D7,E 5,E6,E7, F5,F6,F7, G5,G6,G7, H5,H6,H7,J 5,J6,J7, K5,K6,K7, L5,L6,L7, M5,M6,M7, N4,N8 Ground Ground for the core of the device. VSSQ 5,10,21,26, 55,60,71, 76 5,10,21,26, 55,60,71, 76 - - I/O Ground Ground for the I/O circuitry. CY7C1362B–Pin Definitions (continued) Name TQFP 3-Chip Enable TQFP 2-Chip Enable BGA fBGA I/O Description |
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