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AT45DB021B-SI Datasheet(PDF) 4 Page - ATMEL Corporation |
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AT45DB021B-SI Datasheet(HTML) 4 Page - ATMEL Corporation |
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4 / 33 page  4 AT45DB021B 1937F–DFLSH–10/02 cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked into thedevicefollowed by 24address bits and32don’t care bits. The first five bits of the 24-bit address sequence are reserved for upward and downward compatibility to larger and smaller density devices (see Notes under “Command Sequence for Read/Write Operations” diagram). The next 10 address bits (PA9 - PA0) specify which page of the main memory array to read, and the last nine bits (BA8 -BA0) of the 24-bit address sequence specify the starting byte address within the page. The 32 don’tcare bits that follow the 24 address bits are needed to initialize the read operation. Following the32don’t care bits, additional clock pulses on the SCK pin will result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits, and the reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the begin- ning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR specification. The Continuous Array Read bypasses both data buff- ers and leaves the contents of the buffers unchanged. MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data directly from any one of the 1024 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, an opcode of 52H or D2H must be clocked into the device followed by 24 address bits and 32 don’t care bits. The first five bits of the 24-bit address sequence are reserved bits, the next 10 address bits (PA9 -PA0) specify the page address, and the next nine address bits (BA8-BA0) specify the starting byte address within the page. The 32 don’tcare bits which follow the 24 address bits are sent to initialize the read operation. Following the 32 don’t care bits, additional pulses on SCK result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits and the reading of data. When the end of a page in main memory is reached during a Main Memory Page Read, the device will continue reading at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To perform a Buffer Read, the eight bits of the opcode must be followed by 15 don’tcare bits, nine address bits, and eight don’t care bits. Since the buffer size is 264-bytes, nine address bits (BFA8 -BFA0) are required to specify the first byte of data to be read from the buffer. The CS pin must remain low during the loading of the opcode, the address bits, the don’t care bits and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. |
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