1

PS8689B

08/05/04

Description

PI6CU877 PLL clock driver is developed for Registered DDR2

DIMM applications with 1.8V operation and differential data input

and output levels.

The device is a zero delay buffer that distributes a differential

clock input pair (CLK, CLK) to eleven differential pairs of clock

outputs which includes feedback clock (Y[0:9], Y[0:9]; FBOUT,

FBOUT).

TheclockoutputsarecontrolledbyCLK/CLK,FBOUT,FBOUT,the

OEisLOWtheoutputsexcept FBOUT,FBOUT,aredisabledwhile

the internal PLL continues to maintain its locked-in frequency.

is high, OE will function as described above. When OS is LOW,

grounded, the PLL is turned off and bypassed for test purposes.

When CLK/CLK are logic low, the device will enter a low power

mode.An input logic detection circuit will detect the logic low level

and perform a low power state where all Y[0:9], Y[0:9]; FBOUT,

FBOUT, and PLL are OFF.

PI6CU877 is a high performance, low skew, and low jitter PLL

clock driver, and it is also able to track Spread Spectrum Clocking

(SSC) for reduced EMI.

Features

• PLL clock distribution optimized for DDR2 SDRAM

applications.

• Distributes one differential clock input pair to ten differential

clock output pairs.

• Differential Inputs (CLK, CLK) and (FBIN, FBIN)

• Input OE/OS: LVCMOS

• Differential Outputs (Y[0:9], Y[0:9] and (FBOUT, FBOUT)

• External feedback pins (FBIN, FBIN) are used to

synchronize the outputs to the clock input.

• Packaging (Pb-free & Green available):

– 52-ball VFBGA (NF)

Pin Configuration

PI6CU877

PLL Clock Driver for

1.8V DDR2 Memory

1

2

3

4

5

6

A

B

GND

GND

GND

GND

C

GND

NB

NB

GND

D

OS

E

CK

NB

NB

F

CK

NB

NB

OE

G

AGND

H

GND

NB

NB

GND

J

GND

GND

GND

GND

k