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MK2069-01GI Datasheet(PDF) 10 Page - Integrated Circuit Systems |
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MK2069-01GI Datasheet(HTML) 10 Page - Integrated Circuit Systems |
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10 / 19 page  Line Card Clock Synchronizer MDS 2069-01 H 10 Revision 050203 Integr ated Circuit System s l 525 Ra ce Stree t , Sa n Jose, CA 951 26 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Under ideal conditions, where the VCXO is phase- locked to a low-jitter reference input, loop phase error is typically maintained to within a few nanoseconds. Lock Detection Circuit Diagram If the lock detection circuit is not used, the LDR output may remain unconnected, however the LDC input should be tied high or low. If the PCB was designed to accommodate the RLD and CLD components but the LD output will not be used, RLD can remain unstuffed and CLD can be replaced with a resistor (< 10 kohm). Power Supply Considerations As with any integrated clock device, the MK2069-01 has a special set of power supply requirements: • The feed from the system power supply must be filtered for noise that can cause output clock jitter. Power supply noise sources include the system switching power supply or other system components. The noise can interfere with device PLL components such as the VCO or phase detector. • Each VDD pin must be decoupled individually to prevent power supply noise generated by one device circuit block from interfering with another circuit block. • Clock noise from device VDD pins must not get onto the PCB power plane or system EMI problems may result. This above set of requirements is served by the circuit illustrated in the Recommended Power Supply Connection (next page). The main features of this circuit are as follows: • Only one connection is made to the PCB power plane. • The capacitors and ferrite chip (or ferrite bead) on the common device supply form a lowpass ‘pi’ filter that remove noise from the power supply as well as clock noise back toward the supply. The bulk capacitor should be a tantalum type, 1 µF minimum. The other capacitors should be ceramic type. • The power supply traces to the individual VDD pins should fan out at the common supply filter to reduce interaction between the device circuit blocks. • The decoupling capacitors at the VDD pins should be ceramic type and should be as close to the VDD pin as possible. There should be no via’s between the decoupling capacitor and the supply pin. Lo c k D e te c tio n C irc uit Lo c k Q u a lific a tio n C ounte r (8 up , 1 dow n) VC XO Ph a s e De te c to r Erro r Ou tp u t LD LD C LD R RL D CL D R ESET FV Div id e r Ou tp u t OE L Input Th re s hold s e t to V D D /2 |
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