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SPT7750BCU Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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SPT7750BCU Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 8 page 3 11/30/01 SPT7750 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indi- cates the specific device testing actually per- formed during production and Quality Assur- ance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Unless otherwise noted, all test are pulsed tests; therefore, TJ = TC = TA. LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteri- zation data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. ELECTRICAL SPECIFICATIONS TJ = TC = TA = +25 °C , VEE=–5.2 V, VRB=–2.0 V, VRM=–1.0 V, VRT=0.00 V, ƒCLK=500 MHz, Duty Cycle=50%, unless otherwise specified. TEST TEST SPT7750A SPT7750B PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS Dynamic Performance Spurious Free Dynamic Range ƒIN = 50 MHz I 49 44 dB ƒIN = 250 MHz I 41 36 dB Digital Inputs Input High Voltage (CLK, CLK) I –1.1 –0.7 –1.1 –0.7 V Input Low Voltage (CLK, CLK) I –1.8 –1.5 –1.8 –1.5 V Clock Pulse Width High (tPWH) I 1.0 0.67 1.0 0.67 ns Clock Pulse Width Low (tPWL) I 1.0 0.67 1.0 0.67 ns Digital Outputs Logic 1 Voltage I –1.1 –0.9 –1.1 –0.9 V Logic 0 Voltage I –1.8 –1.5 –1.8 –1.5 V Rise Time 20% to 80% V 450 450 ps Fall Time 20% to 80% V 450 450 ps Power Supply Requirements Voltage VEE IV –4.95 –5.2 –5.45 –4.95 –5.2 –5.45 V Current IEE I 1.05 1.2 1.05 1.2 A Power Dissipation I 5.5 6.25 5.5 6.25 W Typical Thermal Impedance: θJC = +4 °C/W. |
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