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XR16L2750 Datasheet(PDF) 9 Page - Exar Corporation |
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XR16L2750 Datasheet(HTML) 9 Page - Exar Corporation |
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9 / 49 page  XR16L2750 áç áç áç áç 2.25V TO 5.5V DUART WITH 64-BYTE FIFO REV. 1.0.0 9 2.8 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see Figures 18 through 23. 2.9 Crystal Oscillator or External Clock Input The 2750 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not 5V tolerant and so the maximum at the pin should be VCC. For programming details, see “Programmable Baud Rate Generator.” TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER Auto RS485 Mode FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INTA/B Pin NO 0 = a byte in THR 1 = THR empty 0 = FIFO above trigger level 1 = FIFO below trigger level or FIFO empty INTA/B Pin YES 0 = a byte in THR 1 = transmitter empty 0 = FIFO above trigger level 1 = FIFO below trigger level or transmitter empty TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INTA/B Pin 0 = no data 1 = 1 byte 0 = FIFO below trigger level 1 = FIFO above trigger level FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS C1 22-47 pF C2 22-47 pF Y1 1.8432 MHz to 24 MHz R1 0-120 Ω (Optional) R2 500ΚΩ−1 ΜΩ XTAL1 XTAL2 |
Similar Part No. - XR16L2750 |
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Similar Description - XR16L2750 |
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