MT9M131_17 datasheet(33/50 Pages) ONSEMI

Part #	MT9M131

Description	1/3?릋nch SOC 1.3Mp CMOS Digital Image Sensor

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Manufacturer	ONSEMI [ON Semiconductor]

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MT9M131

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33

Table 13. SENSOR CORE REGISTER DESCRIPTIONS (continued)

Bit Field

Read/Write

Bad

Frame

Synced to

Frame Start

Default

(Hex)

Description

R13:0 − 0x00D − Reset

Bit 15

Synchronize

Changes

0: Normal operation, updates changes to registers

that affect image brightness at the next frame

boundary (integration time, integration delay, gain,

horizontal blanking and vertical blanking, window

size, row/column skip, or row mirror.

1: Do not update any changes to these settings until

this bit is returned to “0”. All registers that are

frame synchronized are affected by this bit setting.

0x0

N

0

W

Bit 9

Restart Bad Frames

When set, a forced restart occurs when a bad frame

is detected. This can shorten the delay when waiting

for a good frame because the delay when masking

out a bad frame is the integration time rather than the

full frame time.

0x0

N

0

W

Bit 8

Show Bad Frames

0: Only output good frames (default)

A bad frame is defined as the first frame following

a change to: window size or position, horizontal

blanking, pixel clock speed, zoom, row or column

skip, or mirroring.

1: Output all frames (including bad frames)

0x0

N

0

W

Bit 5

Reset SOC

This reset signal is fed directly to the SOC part of the

chip, and has no functionality in a stand-alone sensor.

0x0

N

0

W

Bit 4

Output Disable

When set, the output signals are tri-stated.

0x0

N

0

W

Bit 3

Chip Enable

0: Stop sensor readout.

1: Normal operation.

When this is returned to “1”, sensor readout restarts

and begins resetting the starting row in a new frame.

To reduce the digital power, the master clock to the

sensor can be disabled or STANDBY can be used.

0x1

N

YM

W

Bit 2

Analog Standby

0: Normal operation (default).

1: Disable analog circuitry.

Whenever this bit is set to “1” the chip enable bit

(bit 3) should be set to “0”.

0x0

N

YM

W

Bit 1

Restart

Setting this bit causes the sensor to abandon the

current frame and start resetting the first row.

The delay before the first valid frame is read out

equals the integration time. This bit always reads “0”.

0x0

N

YM

W

Bit 0

Reset

Setting this bit puts the sensor in reset mode; this

sets the sensor to its default power-up state. Clearing

this bit resumes normal operation.

0x0

N

YM

W

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