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MT9V023 Datasheet(PDF) 9 Page - ON Semiconductor |
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MT9V023 Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 43 page MT9V023 www.onsemi.com 9 OUTPUT DATA TIMING The data output of the MT9V023 is synchronized with the PIXCLK output. When LINE_VALID (LV) is HIGH, one 10-bit pixel datum is output every PIXCLK period. Figure 7. Timing Example of Pixel Data LINE_VALID PIXCLK DOUT(9:0) P0 (9:0) P1 (9:0) P2 (9:0) P3 (9:0) P4 (9:0) Pn−1 (9:0) Pn (9:0) Valid Image Data Blanking Blanking ... ... ... ... The PIXCLK is a nominally inverted version of the master clock (SYSCLK). This allows PIXCLK to be used as a clock to latch the data. However, when column bin 2 is enabled, the PIXCLK is HIGH for one complete master clock master period and then LOW for one complete master clock period; when column bin 4 is enabled, the PIXCLK is HIGH for two complete master clock periods and then LOW for two complete master clock periods. It is continuously enabled, even during the blanking period. Setting R0x72 bit[4] = 1 causes the MT9V023 to invert the polarity of the PIXCLK. The parameters P1, A, Q, and P2 in Figure 8 are defined in Table 4. Figure 8. Row Timing and FRAME_VALID/LINE_VALID Signals P1 A QA QA P2 Number of master clocks FRAME_VALID LINE_VALID ... ... ... Table 4. FRAME TIME Parameters Name Equation Default Timing at 26.66 MHz A Active data time Context A: R0x04 Context B: R0xCC 752 pixel clocks = 752 master = 28.2 μs P1 Frame start blanking Context A: R0x05 - 23 Context B: R0xCD - 23 71 pixel clocks = 71master = 2.66 μs P2 Frame end blanking 23 (fixed) 23 pixel clocks = 23 master = 0.86 μs Q Horizontal blanking Context A: R0x05 Context B: R0xCD 94 pixel clocks = 94 master = 3.52 μs A+Q Row time Context A: R0x04 + R0x05 Context B: R0xCC + R0xCD 846 pixel clocks = 846 master = 31.72 μs V Vertical blanking Context A: (R0x06) x (A + Q) + 4 Context B: (R0xCE) x (A + Q) + 4 38,074 pixel clocks = 38,074 master = 1.43 ms |
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Similar Description - MT9V023_17 |
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