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MT9V024 Datasheet(PDF) 18 Page - ON Semiconductor |
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MT9V024 Datasheet(HTML) 18 Page - ON Semiconductor |
18 / 40 page MT9V024/D www.onsemi.com 18 The sequence is as follows: 1. During frame n, the new integration time is held in the R0x0B or R0D2 live register. 2. Prior to the start of frame (n + 1) readout, the new integration time is transferred to the exposure control module. Integration for each row of frame (n + 1) has been completed using the old integration time. The earliest time that a row can start integrating using the new integration time is immediately after that row has been read for frame (n + 1). The actual time that rows start integrating using the new integration time is dependent on the new value of the integration time. 3. When frame (n + 2) is read out, it is integrated using the new integration time. If the integration time is changed (R0x0B or R0xD2 written) on successive frames, each value written is applied to a single frame; the latency between writing a value and it affecting the frame readout remains at two frames. frame n+1 frame n+2 frame n write new exposure value (Exp “B”) idle idle Exp “A” Exp “A” Exp “B” Exp “B” Exp “B” Readout Exp “B” Readout Exp “B” Readout Exp “B” Readout Exp “A” Readout Exp “A” New image available at output Frame start acti- vates new exposure value (Exp “B”) AEC −sample writes new exposure value (Exp “B”) AEC −sample writes new exposure value (Exp “B”) Figure 22. Latency of Exposure Register in Master Mode Two−wire serial interface (Input) LED_OUT (Output) FRAME_VALID (Output) Exposure Indicator The exposure indicator is controlled by: • R0x1B LED_OUT Control The MT9V024 provides an output pin, LED_OUT, to indicate when the exposure takes place. When R0x1B bit 0 is clear, LED_OUT is HIGH during exposure. By using R0x1B, bit 1, the polarity of the LED_OUT pin can be inverted. High Dynamic Range High dynamic range is controlled by: Table 9. HIGH DYNAMIC RANGE Context A Context B High Dynamic Enable R0x0F[0] R0x0F[8] Shutter Width 1 R0x08 R0xCF Shutter Width 2 R0x09 R0xD0 Shutter Width Control R0x0A R0xD1 V_Step Voltages R0x31−R0x34 R0x39−R0x3C In the MT9V024, high dynamic range (by setting R0x0F, bit 0 or 8 to 1) is achieved by controlling the saturation level of the pixel (HDR or high dynamic range gate) during the exposure period. The sequence of the control voltages at the HDR gate is shown in Figure 23. After the pixels are reset, the step voltage, V_Step, which is applied to HDR gate, is set up at V1 for integration time t1,then to V2 for time t2, then V3 for time t3, and finally it is parked at V4, which also serves as an antiblooming voltage for the photodetector. This sequence of voltages leads to a piecewise linear pixel response, illustrated (approximately) in Figure 23 and in Figure 24. |
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