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MC68HC908QY1 Datasheet(PDF) 4 Page - Motorola, Inc |
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MC68HC908QY1 Datasheet(HTML) 4 Page - Motorola, Inc |
4 / 182 page Revision History MC68HC908QY/QT Family Data Sheet, Rev. 4 4 Freescale Semiconductor The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History (Sheet 1 of 3) Date Revision Level Description Page Number(s) September, 2002 N/A Initial release N/A December, 2002 0.1 1.2 Features — Added 8-pin dual flat no lead (DFN) packages to features list. 19 Figure 1-2. MCU Pin Assignments — Figure updated to include DFN packages. 21 Figure 2-1. Memory Map — Clarified illegal address and unimplemented memory. 27 Figure 2-2. Control, Status, and Data Registers — Corrected bit definitions for Port A Data Register (PTA) and Data Direction Register A (DDRA). 27 Table 13-3. Interrupt Sources — Corrected vector addresses for keyboard interrupt and ADC conversion complete interrupt. 118 Chapter 13 System Integration Module (SIM) — Removed reference to break status register as it is duplicated in break module. 113 11.3.1 Internal Oscillator and 11.3.1.1 Internal Oscillator Trimming — Clarified oscillator trim option ordering information and what to expect with untrimmed device. 92 Figure 11-5. Oscillator Trim Register (OSCTRIM) — Bit 1 designation corrected. 98 Figure 15-13. Monitor Mode Circuit (Internal Clock, No High Voltage) — Diagram updated for clarity. 150 Figure 12-1. I/O Port Register Summary — Corrected bit definitions for PTA7, DDRA7, and DDRA6. 99 Figure 12-2. Port A Data Register (PTA) — Corrected bit definition for PTA7. 100 Figure 12-3. Data Direction Register A (DDRA) — Corrected bit definitions for DDRA7 and DDRA6. 101 Figure 12-6. Port B Data Register (PTB) — Corrected bit definition for PTB1 103 Chapter 9 Keyboard Interrupt Module (KBI) — Section reworked after deletion of auto wakeup for clarity. 83 Chapter 4 Auto Wakeup Module (AWU) — New section added for clarity. 49 Figure 10-1. LVI Module Block Diagram — Corrected LVI stop representation. 87 Chapter 16 Electrical Specifications — Extensive changes made to electrical specifications. 169 17.5 8-Pin Dual Flat No Lead (DFN) Package (Case #1452) — Added case outline drawing for DFN package. 177 Chapter 17 Ordering Information and Mechanical Specifications — Added ordering information for DFN package. 185 January, 2003 0.2 4.2 Features — Corrected third bulleted item. 49 |
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