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MC92314 Datasheet(PDF) 7 Page - Motorola, Inc |
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MC92314 Datasheet(HTML) 7 Page - Motorola, Inc |
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7 / 100 page  System Overview Single Chip DVB-T Demodulator - Rev. 1.3 (11/30/98) MOTOROLA 1-1 SECTION 1 SYSTEM OVERVIEW In this Application Note Motorola’s single chip demodulator and FEC for DVB-T receivers along with the usual application is described. This section covers the overall descriptions as well as an introduction into the DVB-T standard, supporting the understanding of the special features of the OFDM system. 1.1 General Description Before describing the important specialities of the DVB-T system itself the key features of Motorola’s single chip are outlined. • 0.35mm CMOS process at 3.3 V. • 160 pin QFP package • 169 BGA package There are two main sections in the chip, providing the functions necessary to obtain a complete MPEG-2 transport stream out of one real IF-sampled DVB-T signal. The steps necessary are OFDM demodulation and FEC decoding, corresponding to the three separate devices described in Reference [1-4]: Important capabilities of the FFT/OFDM block: • Usable for 8 MHz, 7 MHz and 6 MHz channel bandwidth by adjusting the clock rate. • C/N performance according to Reference [1-1] Annex A with a degradation margin of 3 dB. • Supported DVB-T modulation schemes: QPSK, 16-QAM and 64-QAM. • Automatic lock onto all specified guard interval lengths (1/32, 1/ 16, 1/ 8, 1/ 4). • Data input: 8 Bit TTL compatible 2’s complement or offset binary. • Channel estimation and correction using the pilot carriers. •I2C compatible interface (M-Bus). • Transmission Parameter Signalling (TPS) data is decoded and made available to the system controller via M-Bus. • Processing of one block of 2048 complex samples (i.e. one 2K-OFDM symbol) in 224 ms. • FFT input wordlength 8 bit, output accuracy 12 bit. • Overflow on certain OFDM subcarriers due to co-channel interferes is prevented internally. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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