CY2V995
Document #: 38-07435 Rev. *A
Page 2 of 10
Device Configuration
The outputs of the CY2V995 can be configured to run at
frequencies ranging from 6 MHz to 200 MHz. The feedback
input divider is controlled by the 3-level DS[0:1] pins as
indicated in Table 1.
Notes:
1.
‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up.
2.
A bypass capacitor (0.1
µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
3.
When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4.
Permissible output division ratios connected to FB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by
using an undivided output for FB and setting DS[1:0] to N (N = 1-6, 8, 10, 12).
Pin Description
Pin
Name
I/O[1]
Type
Description
39
REF
I
LVTTL/
LVCMOS
Reference Clock Input.
17
FB
I
LVTTL
Feedback Input.
37
TEST
I
3-Level
When MID or HIGH, disables PLL (except for conditions of note 3). REF
goes to all outputs. Set LOW for normal operation.
2
sOE#
I, PD
LVTTL
Synchronous Output Enable. When HIGH, it stops clock outputs (except
2Q0 and 2Q1) in a LOW state (for PE = H or M) – 2Q0 and 2Q1 may be used
as the feedback signal to maintain phase lock. When TEST is held at MID
level and sOE# is high, the nF[1:0] pins act as output disable controls for
individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
4
PE
I, PU
LVTTL
Selects Positive or Negative Edge Control and High or Low output drive
strength. When LOW / HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. Please see
Table 8.
34, 33, 36, 35,
43, 42, 1, 44
nF[1:0]
I
3-Level
Select frequency of the outputs. Please see Tables 3, 4, 5, and 7.
41
FS
I
3-Level
Selects VCO operating frequency range. Please see Table 6.
26,27,20,21,
13,14,7,8
nQ[1:0]
O
LVTTL
Four banks of two outputs. Please see Table 5 for frequency settings.
32, 31
DS[1:0]
I
3-Level
Select feedback divider. Please see Table 1.
3
PD#
I, PU
LVTTL
Power-down and reference divider control. When LOW, shuts off entire
chip. Please see Table 2 for settings.
30
LOCK
O
LVTTL
PLL lock indication signal. HIGH indicates lock. LOW indicates that the
PLL is not locked and outputs may not be synchronized to the input.
5,6
VDDQ4[2] PWR
Power
Power supply for Bank 4 output buffers. Please see Table 8 for supply
level constraints
15,16
VDDQ3 [2] PWR
Power
Power supply for Bank 3 output buffers. Please see Table 8 for supply
level constraints
19,28
VDDQ1[2] PWR
Power
Power supply for Bank 1 and Bank 2 output buffers. Please see Table 8
for supply level constraints
18,40
VDD[2]
PWR
Power
Power supply for the internal circuitry. Please see Table 8 for supply level
constraints
9-12, 22-25, 38 VSS
PWR
Power
Ground
Table 1. Feedback Divider Settings
DS[1:0]
N-Feedback Input
Divider
Permitted Output Divider
Connected to FB[4]
LL
2
1 or 2
LM
3
1
LH
4
1,2 or 4
ML
5
1 or 2
MM
1
1,2 or 4
MH
6
1 or 2
HL
8
1 or 2
HM
10
1
HH
12
1
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