1Mx36 & 2Mx18 Synchronous SRAM

- 3 -

Rev 2.0

Nov. 2003

K7A321800M

K7A323600M

1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM

The K7A323600M and K7A321800M are 37,748,736-bit

Synchronous Static Random Access Memory designed for

high performance second level cache of Pentium and

Power PC based System.

It is organized as 1M(2M) words of 36(18) bits and inte-

grates address and control registers, a 2-bit burst address

counter and added some new functions for high perfor-

mance cache RAM applications; GW, BW , LBO, ZZ. Write

cycles are internally self-timed and synchronous.

Full bus-width write is done by GW, and each byte write is

performed by the combination of WEx and BW when GW is

nals.

Burst cycle can be initiated with either the address status

processor(ADSP )

or

address

status

cache

control-

ler( ADSC) inputs. Subsequent burst addresses are gener-

ated internally in the system

′s burst sequence and are

controlled by the burst address advance(ADV) input.

LBO

pin

is

DC

operated

and

determines

burst

sequence(linear or interleaved).

ZZ pin controls Power Down State and reduces Stand-by

current regardless of CLK.

The K7A323600M and K7A321800M are fabricated using

SAMSUNG

′s high performance CMOS technology and is

available in a 100pin TQFP package. Multiple power and

ground pins are utilized to minimize ground bounce.

GENERAL DESCRIPTION

FEATURES

LOGIC BLOCK DIAGRAM

• Synchronous Operation.

• 2 Stage Pipelined operation with 4 Burst.

• On-Chip Address Counter.

• Self-Timed Write Cycle.

• On-Chip Address and Control Registers.

• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O.

• 5V Tolerant Inputs Except I/O Pins.

• Byte Writable Function.

• Global Write Enable Controls a full bus-width write.

• Power Down State via ZZ Signal.

• LBO Pin allows a choice of either a interleaved burst or a linear

burst.

• Three Chip Enables for simple depth expansion with No Data Con-

tention only for TQFP ; 2cycle Enable, 1cycle Disable.

• Asynchronous Output Enable Control.

• ADSP, ADSC, ADV Burst Control Pins.

• TTL-Level Three-State Output.

• 100-TQFP-1420A Package

• Operating in commeical and industrial temperature range.

CLK

LBO

ADV

ADSC

ADSP

GW

BW

WEx

OE

ZZ

BURST CONTROL

LOGIC

BURST

1Mx36 , 2Mx18

ADDRESS

CONTROL

OUTPUT

DATA-IN

ADDRESS

COUNTER

MEMORY

ARRAY

REGISTER

REGISTER

BUFFER

LOGIC

A

REGISTER

FAST ACCESS TIMES

PARAMETER

Symbol

-25

-20

-14

Unit

Cycle Time

tCYC

4.0

5.0

7.2

ns

Clock Access Time

tCD

2.6

3.1

4.0

ns

Output Enable Access Time

tOE

2.6

3.1

4.0

ns

DQPa ~ DQPd

(x=a,b,c,d or a,b)

DQPa,DQPb