M25P64-VMF6T datasheet(10/38 Pages) STMICROELECTRONICS

Part #	M25P64-VMF6T

Description	64 Mbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface

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M25P64

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Hold Condition

The Hold (HOLD) signal is used to pause any se-

rial communications with the device without reset-

ting the clocking sequence. However, taking this

signal Low does not terminate any Write Status

Register, Program or Erase cycle that is currently

in progress.

To enter the Hold condition, the device must be

selected, with Chip Select (S) Low.

The Hold condition starts on the falling edge of the

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) being Low (as shown in Fig-

ure 7.).

The Hold condition ends on the rising edge of the

Hold (HOLD) signal, provided that this coincides

with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial

Clock (C) being Low, the Hold condition starts af-

ter Serial Clock (C) next goes Low. Similarly, if the

rising edge does not coincide with Serial Clock (C)

being Low, the Hold condition ends after Serial

Clock (C) next goes Low. (This is shown in Figure

7.).

During the Hold condition, the Serial Data Output

(Q) is high impedance, and Serial Data Input (D)

and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip

Select (S) driven Low, for the whole duration of the

Hold condition. This is to ensure that the state of

the internal logic remains unchanged from the mo-

ment of entering the Hold condition.

If Chip Select (S) goes High while the device is in

the Hold condition, this has the effect of resetting

the internal logic of the device. To restart commu-

nication with the device, it is necessary to drive

Hold (HOLD) High, and then to drive Chip Select

(S) Low. This prevents the device from going back

to the Hold condition.

Figure 7. Hold Condition Activation

AI02029D

HOLD

C

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

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