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M366S1723ET Datasheet(PDF) 4 Page - Samsung semiconductor |
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M366S1723ET Datasheet(HTML) 4 Page - Samsung semiconductor |
4 / 26 page 64MB, 128MB, 256MB Unbuffered DIMM Rev. 1.3 February 2004 SDRAM * SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. PIN CONFIGURATIONS (Front side/back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 **CS0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD **CLK0 VSS DU **CS2 DQM2 DQM3 DU VDD NC NC CB2 CB3 VSS DQ16 DQ17 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VDD DQ20 NC *VREF **CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **CLK2 NC NC SDA SCL VDD Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 **CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD **CLK1 *A12 VSS **CKE0 **CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VDD DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **CLK3 NC SA0 SA1 SA2 VDD Pin Description Pin Name Function Pin Name Function A0 ~ A11 Address input (Multiplexed) DQM0 ~ 7 DQM BA0 ~ BA1 Select bank VDD Power supply (3.3V) DQ0 ~ DQ63 Data input/output VSS Ground CB0 ~ CB7 Check bit (Data-in/data-out) VREF Power supply for reference CLK0 ~ 3 Clock input REGE Register enable CKE0, CKE1 Clock enable input SDA Serial data I/O CS0 ~ CS3 Chip select input SCL Serial clock RAS Row address strobe SA0 ~ 2 Address in EEPROM CAS Colume address strobe DU Don ′t use WE Write enable NC No connection 1. * These pins are not used in this module. 2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD. 3. Pins 21,22,52,53,105,106,136,137are used only ECC(x72) Module. 4. ** About these pins, Refer to the Block Diagram of each. Note : |
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