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M29W400BB90M1 Datasheet(PDF) 2 Page - STMicroelectronics |
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M29W400BB90M1 Datasheet(HTML) 2 Page - STMicroelectronics |
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2 / 25 page  M29W400BT, M29W400BB 2/25 Figure 2. TSOP Connections DQ3 DQ9 DQ2 A6 DQ0 W A3 RB DQ6 A8 A9 DQ13 A17 A10 DQ14 A2 DQ12 DQ10 DQ15A–1 VCC DQ4 DQ5 A7 DQ7 NC NC AI02935 M29W400BT M29W400BB 12 1 13 24 25 36 37 48 DQ8 NC NC A1 NC A4 A5 DQ1 DQ11 G A12 A13 A16 A11 BYTE A15 A14 VSS E A0 RP VSS Figure 3. SO Connections G DQ0 DQ8 A3 A0 E VSS A2 A1 A13 VSS A14 A15 DQ7 A12 A16 BYTE DQ15A–1 DQ5 DQ2 DQ3 VCC DQ11 DQ4 DQ14 A9 W RB A4 NC RP A7 AI02936 M29W400BT M29W400BB 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 DQ1 DQ9 A6 A5 DQ6 DQ13 44 39 38 37 36 35 34 33 A11 A10 DQ10 21 DQ12 40 43 1 42 41 A17 A8 Table 1. Signal Names A0-A17 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or Address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select VCC Supply Voltage VSS Ground NC Not Connected Internally SUMMARY DESCRIPTION The M29W400B is a 4 Mbit (512Kb x8 or 256Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be per- formed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The M29W400B is fully backward compatible with the M29W400. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are writ- ten to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. |
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