Electronic Components Datasheet Search |
|
MAX9388EEP Datasheet(PDF) 11 Page - Maxim Integrated Products |
|
MAX9388EEP Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 14 page Applications Information Output Termination Terminate the outputs through 50 Ω to VCC - 2V or use equivalent Thevenin terminations. Terminate each Q and Q output with identical termination on each for min- imal distortion. When a single-ended signal is taken from the differential output, terminate both Q and Q. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device’s total thermal limits should be observed. Supply Bypassing Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1µF and 0.01µF capacitors. For PECL, bypass each VCC to VEE. For ECL, bypass each VEE to VCC. Place the capacitors as close to the device as possible with the 0.01µF capacitor closest to the device pins. Use multiple vias when connecting the bypass capaci- tors to ground. When using the VBB1 or VBB2 reference outputs, bypass each one with a 0.01µF ceramic capacitor to VCC. If the VBB1 or VBB2 reference outputs are not used, they can be left open. Traces Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reduc- ing signal reflections and skew, and increasing com- mon-mode noise immunity. Signal reflections are caused by discontinuities in the 50 Ω characteristic impedance of the traces. Avoid dis- continuities by maintaining the distance between differ- ential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces. Chip Information TRANSISTOR COUNT: 583 PROCESS: Bipolar Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers ______________________________________________________________________________________ 11 VBB1 VBB2 VCC VEE VCC VEE MUX 150k Ω 150k Ω 120k Ω 150k Ω 250k Ω D0 D0 D1 D1 D2 D2 D3 D3 D4** SEL0 SEL1 SEL2** D4** Q0 (Q*) Q0 (Q*) MAX9386 (*) DOES NOT HAVE Q1 AND Q1 OUTPUTS, AND MAX9388 (**) DOES NOT HAVE D4, D4, AND SEL2 INPUTS. Q1* Q1* D_ D_ MAX9386 MAX9387 MAX9388 VEE Functional Block Diagram Ordering Information (continued) PART TEMP RANGE PIN- PACKAGE SELECTION MAX9387EUG -40 °C to +85°C 24 TSSOP 5:1 mux with 2 output buffers MAX9387EEG* -40 °C to +85°C 24 QSOP 5:1 mux with 2 output buffers MAX9388EUP -40 °C to +85°C 20 TSSOP 4:1 mux with 1 output buffer MAX9388EEP* -40 °C to +85°C 20 QSOP 4:1 mux with 1 output buffer *Future product—contact factory for availability. |
Similar Part No. - MAX9388EEP |
|
Similar Description - MAX9388EEP |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |