November 2004

11

MIC280

MIC280

Micrel

using the A.R.A. if the host system does not implement the

A.R.A protocol. Figure 4 and Figure 5 illustrate these two

methods of responding to MIC280 interrupts.

Since temperature-to-digital conversions continue while /INT

isasserted,themeasuredtemperaturecouldchangebetween

the MIC280’s assertion of /INT and the host’s response. It

is good practice for the interrupt service routine to read the

value in TEMPx, to verify that the over-temperature or under-

temperature condition still exists. In addition, more than one

temperature event may have occurred simultaneously or in

rapid succession between the assertion of /INT and servic-

ing of the MIC280 by the host. The interrupt service routine

should allow for this eventuality. At the end of the interrupt

service routine, the interrupt enable bits should be reset to

permit future interrupts.

Reading the Result Registers

All MIC280 registers are eight bits wide and may be accessed

using the standard Read_Byte protocol. The temperature

result for the local zone, zone 0, is a single 8-bit value in

register TEMP0. A single Read_Byte operation by the host

is sufficient for retrieving this value. The temperature result

for the remote zone is a twelve-bit value split across two

eight-bit registers, TEMP1h and TEMP1l. A series of two

Read_Byte operations are needed to obtain the entire twelve-

bit temperature result for zone 1. It is possible under certain

conditions that the temperature result for zone 1 could be

updated between the time TEMP1l or TEMP1h is read and

the companion register is read. In order to insure coherency,

TEMP1h supports the use of the Read_Word protocol for ac-

cessing both TEMP1h and TEMP1l with a single operation.

This insures that the values in both result registers are from

the same ADC cycle. This is illustrated in Figure 3 above.

Read_Word operations are only supported for TEMP1h:

TEMP1l, i.e., only for command byte values of 01h.

Polling

The MIC280 may either be polled by the host, or request

the host’s attention via the /INT pin. In the case of polled

operation, the host periodically reads the contents of STA-

TUS to check the state of the status bits. The act of reading

STATUS clears it. If more than one event that sets a given

status bit occurs before the host polls STATUS, only the fact

that at least one such event has occurred will be apparent

to the host. For polled systems, the global interrupt enable

bit should be clear (IE = 0). This will disable interrupts from

the MIC280 (prevents the /INT pin from sinking current).

For interrupt-driven systems, IE must be set to enable the

/INT output.

Shutdown Mode

Puttingthedeviceintoshutdownmodebysettingtheshutdown

bit in the configuration register will unconditionally deassert

/INT, clear STATUS, and purge the fault queues. Therefore,

this should not be done before completing the appropriate

interrupt service routine(s). No other registers will be affected

by entering shutdown mode. The last temperature readings

will persist in the TEMPx registers.

The MIC280 can be prevented from entering shutdown

mode using the shutdown lockout bit in the lock register. If

L3 in LOCK is set while the MIC280 is in shutdown mode,

it will immediately exit shutdown mode and resume normal

operation. It will not be possible to subsequently re-enter

shutdown mode. If the reset bit is set while the MIC280 is

shut down, normal operation resumes from the reset state.

(see below)

Warm Resets

The MIC280 can be reset to its power-on default state during

operation by setting the RST bit in the configuration register.

When this bit is set, /INT will be deasserted, the fault queues

willbepurged,thelimitregisterswillberestoredtotheirnormal

power-on default values, and anyA/D conversion in progress

will be halted and the results discarded. This includes reset-

ting bits L3 - L0 in the security register, LOCK. The state of

the MIC280 following this operation is indistinguishable from

a power-on reset. If the reset bit is set while the MIC280 is

shut down, the shutdown bit is cleared and normal operation

resumes from the reset state.

If bit 4 of LOCK, the Warm Reset Lockout Bit, is set, warm

resets cannot be initiated, and writes to the RST bit will be

completely ignored. Setting L4 while the MIC280 is shut

down will result in the device exiting shutdown mode and

resuming normal operation, just as if the shutdown bit had

been cleared.

EVENT

CONDITION

MIC280 RESPONSE*

Data ready

A/D conversions complete for both zones; result

Set S7, clear IM7, assert /INT

registers updated; state of /INT updated

Over-temperature, remote

([TEMP1h:TEMP1l]) > CRIT1

Set S1, assert /INT

Over-temperature, local

TEMP0 > CRIT0

Set S0, assert /INT

High temperature, remote

([TEMP1h:TEMP1l]) > THIGH1h:THIGH1l]**

Set S4, clear IM4, assert /INT

High temperature, local

TEMP0 > THIGH0**

Set S6, clear IM6, assert /INT

Low temperature, remote

( [TEMP1h:TEMP1l]) < TLOW1h:TLOW1l]**

Set S3, clear IM3, assert /INT

Low temperature, local

TEMP0 < TLOW0**

Set S5, clear IM5, assert /INT

Diode fault

T1 open or T1 shorted to VDD or GND

Set S2, clear IM2, assert /INT

* Assumes interrupts enabled. **CONDITION must be true for Fault_Queue conversions to be recognized.

Table 6: MIC280 Temperature Events