DS2438 - 2.3

NJ88C24

Frequency Synthesiser with non-resettable counters

The NJ88C24 is a synthesiser circuit fabricated on the GPS

CMOS process and is capable of achieving high sideband

attenuation and low noise performance. It contains a reference

oscillator, 11-bit programmable reference divider, digital and

sample-and-hold comparators, 10-bit programmable ‘M’ counter,

7-bit programmable ‘A’ counter and the necessary control and

latch circuitry for accepting and latching the input data.

Data is presented serially under external control from a

suitable microprocessor. Although 28 bits of data are initially

required to program all counters, subsequent updating can be

abbreviated to 17 bits, when only the ‘A’ and‘M’ counters require

changing.

The NJ88C24 is intended to be used in conjunction with a

two-modulus prescaler such as the SP8710 or SP8705 series

to produce a universal binary coded synthesiser for up to

1100MHz operation.

Fig.1 Pin connections - top view (not to scale)

FEATURES

DG16, DP16

MP18

Fig.2 Block diagram

7 (9)

8 (10)

10 (12)

12 (14)

11 (13)

4 (5)

6 (7)

5 (6)

OSC IN

OSC OUT

DATA

ENABLE

CLOCK

REFERENCE COUNTER

(11BITS)

LATCH 6

LATCH 7

LATCH 8

LATCH 1

LATCH 2

LATCH 3

‘M’ COUNTER

(10 BITS)

‘M’ REGISTER

‘R’ REGISTER

CONTROL LOGIC

LATCH 4

LATCH 5

‘A’ COUNTER

(7 BITS)

‘A’ REGISTER

42

SAMPLE/HOLD

PHASE

DETECTOR

FREQUENCY/

PHASE

DETECTOR

PDA

PDB

LOCK DETECT (LD)

MODULUS

CONTROL

OUTPUT (MC)

1 (1)

2 (2)

3 (4)

14 (16)

RB

CAP

CH

15

17

16

(17)

(15)

(18)

ORDERING INFORMATION

NJ88C24 MA DG Ceramic DIL Package

NJ88C24 MA DP Plastic DIL Package

NJ88C24 MA MP Miniature Plastic DIL Package

20·5V to 7V

7V

255

°C to 1125°C

(DP and MP packages)

265

°C to 1150°C

(DG package)

ABSOLUTE MAXIMUM RATINGS

Input voltage

Open drain output, LD pin:

All other pins:

Storage temperature:

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

NJ88C24

PDA

PDB

NC

LD

NC

OSC IN

CH

RB

MC

CAP

ENABLE

CLOCK

DATA

NC

OSC OUT

CH

RB

MC

CAP

ENABLE

CLOCK

DATA

NC

PDA

PDB

LD

FIN

OSC IN

OSC OUT

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

NJ88C24