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VG36644041DTL-6 Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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VG36644041DTL-6 Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
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8 / 69 page  Document :1G5-0177 Rev.2 Page 8 VIS VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM A.C. Characteristics (Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 0.3V , VSS = VSSQ = 0V, unless otherwise noted) Notes 1. -6 grade is available only on 4MX16 option. 2. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter. Parameter Sym- bol Limits Unit Note -6 *1 -7 -7L -8H Min Max Min Max Min Max Min Max CLK cycle time CL = 3 tCK3 6 7 7.5 8 ns CL = 2 tCK2 7.5 7.5 10 10 ns CLK to valid output delay CL = 3 tAC3 5 5.4 5.4 6 ns *2 CL = 2 tAC2 6 6 6 6 ns *2 CLK high pulse width tCH 2.5 2.5 2.5 3 ns CLK low pulse width tCL 2.5 2.5 2.5 3 ns CKE setup time tCKS 1.5 1.5 1.5 2 ns CKE hold time tCKH 0.8 0.8 0.8 1 ns Address setup time tAS 1.5 1.5 1.5 2 ns Address hold time tAH 0.8 0.8 0.8 1 ns Command setup time tCMS 1.5 1.5 1.5 2 ns Command hold time tCMH 0.8 0.8 0.8 1 ns Data input setup time tDS 1.5 1.5 1.5 2 ns Data input hold time tDH 0.8 0.8 0.8 1 ns Output data hold time CL = 3 tOH3 2.5 2.7 2.7 3 ns *2 CL = 2 tOH2 2.5 2.7 3 3 ns *2 CLK to output in low - Z tLZ 0 0 0 0 ns CLK to output in H - Z tHZ 2.5 5 2.7 5.4 2.7 5.4 3 6 ns ROW cycle time tRC 60 63 67.5 70 ns ROW active time tRAS 42 100K 42 100K 45 100K 50 100K ns RAS to CAS delay tRCD 18 20 20 20 ns Row precharge time tRP 15 15 20 20 ns Row active to active delay tRRD 12 14 15 20 ns Data in to precharge tDPL 12 14 15 20 ns Transition time tT 1 10 1 10 1 10 1 10 ns Mode reg. set cycle tRSC 2 2 2 2 tck Refresh time tREF 64 64 64 64 ms ± |
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