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AD9847AKST Datasheet(PDF) 9 Page - Analog Devices |
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AD9847AKST Datasheet(HTML) 9 Page - Analog Devices |
9 / 28 page REV. A AD9847 –9– SERIAL INTERFACE TIMING SDATA A0 A1 A2 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 XX XX SCK SL A3 NOTES 1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. 2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS. 3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED. 4. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE. 5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER. VD HD SL UPDATED VD/HD UPDATED tDS tDH tLS tLH Figure 3a. Serial Write Operation SDATA A0 A1 A2 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 SCK SL A3 NOTES 1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 6-BIT DATA-WORDS. 3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA-WORD (ALL SIX BITS MUST BE WRITTEN). 4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE. D0 D1 D2 D3 D4 D5 D0 ... ... ... DATA FOR STARTING REGISTER ADDRESS DATA FOR NEXT REGISTER ADDRESS D2 D1 Figure 3b. Continuous Serial Write Operation COMPLETE REGISTER LISTING Table I. SL Updated Registers Register Description Register Description oprmode AFE Operation Modes ctlmode AFE Control Modes preventpdate Prevents Loading of VD-Updated Registers readback Enables Serial Register Readback Mode vdhdpol VD/HD Active Polarity fieldval Internal Field Pulse Value hblkretime Retimes the H1 hblk to Internal Clock tgcore_rstb Reset Bar Signal for Internal TG Core h12pol H1/H2 Polarity Control h1posloc H1 Positive Edge Location h1negloc H1 Negative Edge Location h1drv H1 Drive Current h2drv H2 Drive Current h3drv H3 Drive Current h4drv H4 Drive Current rgpol RG Polarity rgposloc RG Positive Edge Location rgnegloc RG Negative Edge Location rgdrv RG Drive Current shpposloc SHP Sample Location shdposloc SHD Sample Location NOTES All addresses and default values are expressed in hexadecimal. All registers are VD/HD updated as shown in Figure 3a, except for those that are SL updated. |
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